DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 6, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kanaya (United States Patent Application Publication No. US 2008/0217669 A1, hereinafter “Kanaya”).
In reference to claim 1, Kanaya discloses a structure which meets the claim. An annotated version of fig. 1 of Kanaya is provided below. Fig. 1 of Kanaya discloses an integrated circuit structure comprising a first capacitor structure (M00, M01) with a plurality of capacitors (M00, M01) disposed over a semiconductor substrate. A second capacitor structure (DC00, DC01) is adjacent to the first capacitor structure (M00, M01). The examiner notes that the currently filed specification, in fig. 4, uses conductive lines (4082, 4084) as plates (p. 9, paragraph 38). Thus annotated fig. 1 of Kanaya shows that there is a first conductive plate in the form of a conductive line extending into and out of the page (p. 2, paragraph 31). Fig. 1 also shows that the first conductive plate is disposed over a first end of the second capacitor structure (DC00, DC01). The first conductive plate has a lateral side facing a lateral side of each of the first (M00, M01) and second (DC00, DC01) capacitor structures. There is a second conductive plate disposed over and across at least one of the first capacitor structure (M00, M01) and the second capacitor structure (DC00, DC01).
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In reference to claim 6, Kanaya discloses a structure which meets the claim. An annotated version of fig. 1 of Kanaya is provided below. Fig. 1 of Kanaya discloses an integrated circuit structure which comprises a capacitor structure (M00) disposed in a first layer over a semiconductor substrate. Kanaya discloses a dummy capacitor (DC01) which has a lower dummy electrode made of the metal iridium (p. 4, paragraph 49). Thus there is a dummy metal structure (DC01) in the form of an iridium dummy lower electrode for the dummy capacitor (DC01) which is adjacent to the capacitor structure (M00) in the first layer. The examiner notes that the currently filed specification, in fig. 4, uses conductive lines (4082, 4084) as plates (p. 9, paragraph 38). Thus annotated fig. 1 of Kanaya shows that there is a first conductive plate in the form of a conductive line extending into and out of the page (p. 2, paragraph 31). Fig. 1 shows that the first conductive plate is disposed adjacent to the dummy metal structure (DC01). Each of the capacitor structure (M00) and the first conductive plate has a side facing a side of the dummy metal structure (DC01). There is a second conductive plate (M2) disposed in a second layer over the semiconductor substrate different from the first layer. The second conductive player (M2) extends from a first end of the dummy metal structure (DC01) to a second end of the dummy metal structure (DC01) opposite to the first end.
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In reference to claim 19, Kanaya discloses a method which meets the claim. An annotated version of fig. 1 of Kanaya is provided below. Fig. 1 of Kanaya discloses a method of manufacturing an integrated circuit structure which comprises forming a first capacitor structure (M01) over a semiconductor substrate. Fig. 2 shows that a second capacitor structure (M00) is formed adjacent to and connected to the first capacitor structure (M00) by their common lower electrode. The examiner notes that the currently filed specification, in fig. 4, uses conductive lines (4082, 4084) as plates (p. 9, paragraph 38). Thus annotated fig. 1 of Kanaya shows that there is a first conductive plate in the form of a conductive line extending into and out of the page (p. 2, paragraph 31). Fig. 1 shows that the first conductive plate is formed on a first end of the second capacitor structure (M00). The first conductive plate has a lateral side facing a lateral side of each of the first (M01) and second (M00) capacitor structures. There is a second conductive plate (M2) that is formed and disposed over at least one of the first capacitor structure (M01) and the second capacitor structure (M00).
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Allowable Subject Matter
Claims 2-5, 7-18, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: in the examiner’s opinion, it would not be obvious to implement an integrated circuit structure which comprises first and second capacitor structures disposed over a semiconductor substrate that are adjacent to each other such that the first capacitor structure has a plurality of capacitors in combination with the suggested positions of first, second, and third conductive plates and the specific coupling between the first and third conductive plates as required by the applicant in claims 2 and 5.
In the examiner’s opinion, it would also not be obvious to implement an integrated circuit structure which comprises a capacitor structure and a dummy metal structure disposed over a semiconductor substrate that are adjacent to each other with a first conductive plate adjacent to the dummy metal structure such that the capacitor structure and the first conductive plate each has a side facing a side of the dummy metal structure in combination with the suggested position of a second conductive plate and the specific connection structures between the first and second conductive plates as required by the applicant in claim 7.
In the examiner’s opinion, it would also not be obvious to implement a method of manufacturing an integrated circuit structure which comprises forming first and second capacitor structures over a semiconductor substrate that are adjacent and connected to each other in combination with the suggested positions of first, second, and third conductive plates and the specific coupling between the first and third conductive plates as required by the applicant in claim 20.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEVIN QUINTO whose telephone number is (571)272-1920. The examiner can normally be reached Monday-Friday, 9-5:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KEVIN QUINTO/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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