Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the CON application No. 18/769,417 filed on July 11, 2024.
Information Disclosure Statement
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Double Patenting
4. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
5. Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,087,597 B2 (Liu et al.). Although the claims at issue are not identical, they are not patentably distinct from each other because each of the instant limitations are recited in or obvious from claims 1-20 of U.S. Patent No. 12,087,597 B2.
Regarding independent claim 1, Liu et al. recites a semiconductor structure, comprising:
a first die (claim 1, line 2);
a plurality of first conductive vias adjacent to the first die (claim 1, line 4);
a plurality of second conductive vias disposed over the plurality of first conductive vias, each of the plurality of second conductive vias corresponding to one of the plurality of first conductive vias (claim 1, lines 5-8);
a plurality of third conductive vias disposed over the first die (claim 1, lines 9-10); and
a molding material encapsulating the first die, the plurality of first conductive vias, the plurality of second conductive vias and the plurality of third conductive vias (claim 1, lines 11-14),
wherein a first width of each of the plurality of first conductive vias, a second width of each of the plurality of second conductive vias and a third width of the plurality of third conductive vias are different from each other (claim 1, lines 15-17, claim 17, lines 1-4).
Regarding claim 2, Liu et al. recites, wherein top surfaces of the plurality of first conductive vias are level with a top surface of the first die (claim 2, lines 1-3).
Regarding claim 3, Liu et al. recites, further comprising:
a second die disposed over the first die (claim 1, lines 3);
wherein the plurality of third conductive vias are disposed adjacent to the second die (claim 1, lines 9-10), and a top surface of the second die is level with top surfaces of the plurality of second conductive vias or top surfaces of the plurality of third conductive vias (claim 3, lines 1-4).
Regarding claim 4, Liu et al. recites, wherein a stepped shape is formed around an interface between each of the plurality of first conductive vias and corresponding one of the plurality of second conductive vias (claim 4, lines 1-4).
Regarding claim 5, Liu et al. recites, wherein the first width of each of the first conductive via is greater than the second width of each of the second conductive vias (claim 1, lines 15-17).
Regarding claim 6, Liu et al. recites, wherein a distance between adjacent of the plurality of first conductive vias is substantially equal to or greater than a distance between adjacent of the plurality of second conductive vias (claim 6, lines 1-4).
Regarding claim 7, Liu et al. recites, a semiconductor structure, comprising:
a first die over a redistribution layer (RDL) (claim 7, line 2);
a plurality of first conductive vias adjacent to the first die (claim 7, line 4);
a plurality of second conductive vias disposed over the plurality of first conductive vias, each of the plurality of second conductive vias corresponding to one of the plurality of first conductive vias (claim 7, lines 5-8);
a plurality of third conductive vias disposed over the first die (claim 7, lines 9-10); and
a molding material encapsulating the first die, the plurality of first conductive vias, the plurality of second conductive vias and the plurality of third conductive vias (claim 7, lines 11-14), and disposed in contiguous manner from an upper surface of the RDL to an upper surface of each of the plurality of second conductive vias (claim 15, lines 11-16, claim 19, lines 8-9).
Regarding claim 8, Liu et al. recites, further comprising:
a second die disposed over the first die and adjacent to the plurality of third conductive vias (claim 7, lines 3, 9-10);
wherein a thickness of the second die is substantially equal to a height of the plurality of third conductive vias (claim 8, lines 1-3).
Regarding claim 9, Liu et al. recites, wherein the molding material includes a same material between the first die and the plurality of first conductive vias and between the plurality of third conductive vias (claim 9, lines 1-4).
Regarding claim 10, Liu et al. recites, wherein the plurality of third conductive vias are electrically coupled to the first die (claim 10, lines 1-3).
Regarding claim 11, Liu et al. recites, wherein the first die includes:
a first substrate (claim 11, line 3);
a first conductive pad over the first substrate (claim 11, line 4);
a first passivation layer over the first conductive pad (claim 11, line 5); and
a die film attached to the first substrate on a side of the first substrate opposite to the first conductive pad (claim 11, lines 6-7).
Regarding claim 12, Liu et al. recites, further comprising:
a plurality of die connectors electrically connected to the first conductive pad and disposed over the first passivation layer of the first die (claim 12, lines 3-5).
Regarding claim 13, Liu et al. recites, wherein the plurality of third conductive vias are electrically coupled to the plurality of die connectors (claim 13, lines 1-3).
Regarding claim 14, Liu et al. recites, wherein a stepped shape is formed around an interface between each of the plurality of first conductive vias and the corresponding one of the plurality of second conductive vias (claim 14, lines 1-4).
Regarding independent claim 15, Liu et al. recites a semiconductor structure, comprising:
a first die (claim 15, line 2);
a plurality of first conductive vias adjacent to the first die (claim 15, line 3);
a plurality of second conductive vias disposed over the plurality of first conductive vias, each of the plurality of second conductive vias corresponding to one of the plurality of first conductive vias (claim 15, lines 5-8); and
a molding material encapsulating the first die, the plurality of first conductive vias, and the plurality of second conductive vias, and disposed in a contiguous manner from a location between the plurality of the second conductive vias to another location between the plurality of first conductive vias (claim 15, lines 11-17).
Regarding claim 16, Liu et al. recites, further comprising:
a second die disposed over the first die (claim 15, line 3); and
a plurality of third conductive vias disposed over of the first die and adjacent to the second die (claim 15, lines 9-10);
wherein the second die is disposed between the plurality of third conductive vias (claim 16, lines 1-3), and the molding material further encapsulates the second die and the plurality of third conductive vias (claim 15, lines 11-13).
Regarding claim 17, Liu et al. recites, wherein a width the plurality of third conductive vias is substantially equal to or less than the width of each of the plurality of second conductive vias (claim 17, lines 1-4).
Regarding claim 18, Liu et al. recites, wherein a stepped shape is formed around an interface between each of the plurality of first conductive vias and the corresponding one of the plurality of second conductive vias (claim 18, lines 1-4).
Regarding claim 19, Liu et al. recites, further comprising:
a first redistribution layer (RDL) disposed under the first die and the plurality of the first conductive dies (claim 19, lines 3-4); and
a second RDL disposed over the plurality of second conductive vias (claim 19, lines 5-6),
wherein the molding material is disposed between the first RDL and the second RDL (claim 19, line 8).
Regarding claim 20, Liu et al. recites, wherein a distance between adjacent of the plurality of first conductive vias is less than a distance between adjacent of the plurality of second conductive vias (claim 20, lines 1-4).
Conclusion
6. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DIDARUL MAZUMDER whose telephone number is (571)272-8823. The examiner can normally be reached M-F 9-5.
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7. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DIDARUL A MAZUMDER/Primary Examiner, Art Unit 2812
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