DETAILED ACTION
This action is responsive to the application No. 18/769,425 filed on July 11, 2024.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species II/IIA, corresponding to claims 1-5, 9, 21-23, and 25-29, in the reply filed on August 11, 2026, is acknowledged.
Claim Objections
Claims 30-35 are objected to because of the following informalities:
In claim 30, line 7, “coves” should be changed to -- covers --.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 21-23 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 21 recites a third TIM layer over the first semiconductor die having no written description support. In Fig. 5, the first die is 120, the third TIM layer is 146 and 146 is not “over” 120.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 25-27 and 29 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gonsalves et al. (US 6,212,074).
(Re Claim 25) Gonsalves teaches a semiconductor package structure comprising (see Fig. 2):
a first semiconductor die (10-6) and a second semiconductor die (10-4) arranged along a first direction (left-right); and
a multi-TIM structure (100+40) over the first semiconductor die and the second semiconductor die, the multi-TIM structure comprising at least a first TIM layer (40 on left), a second TIM layer (100) and a third TIM layer (40 on right), wherein the first TIM layer, the second TIM layer and the third TIM layer are arranged along the first direction (left-right), wherein a first portion of an upper surface of the first semiconductor die is covered by the first TIM layer (edge of upper surface of 10-6 covered by 40 on left), and a second portion of the upper surface of the first semiconductor die is covered by the second TIM layer (remainder of upper surface is covered by 100).
(Re Claim 26) wherein a first portion of the upper surface of the second semiconductor die (10-4) is covered by the first TIM layer (40), and a second portion of the upper surface of the second semiconductor die is covered by the third TIM layer (covered by 40 on right side when viewed from the right side noting “covered” does not require contact or a particular direction or orientation).
(Re Claim 27) wherein a surface area of the first TIM layer is greater than a surface area of the second TIM layer and greater than a surface area of the third TIM layer (as recited “a surface area” for each TIM layer may be arbitrarily selected to meet the claimed relationships, a surface area may be ascribed to any portion(s) of the surface area).
(Re Claim 29) wherein a thickness of the first TIM layer, a thickness of the second TIM layer and a thickness of the third TIM layer are substantially the same (Fig. 2 showing the thicknesses are substantially the same).
Claims 25-29 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Arvelo et al. (US 2010/019377).
(Re Claim 25) Arvelo teaches a semiconductor package structure comprising (see Fig. 5B):
a first semiconductor die (201) and a second semiconductor die (220 or 240) arranged along a first direction (vertical direction); and
a multi-TIM structure over the first semiconductor die and the second semiconductor die, the multi-TIM structure comprising at least a first TIM layer, a second TIM layer and a third TIM layer, wherein the first TIM layer, the second TIM layer and the third TIM layer are arranged along the first direction (see annotated figure below, the TIM layers are arranged in a vertical direction), wherein a first portion of an upper surface of the first semiconductor die is covered by the first TIM layer, and a second portion of the upper surface of the first semiconductor die is covered by the second TIM layer (the upper surface of 201 is covered by portions of all of the TIM layers, covered does not require contact or any particular direction or orientation).
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(Re Claim 26) wherein a first portion of the upper surface of the second semiconductor die is covered by the first TIM layer, and a second portion of the upper surface of the second semiconductor die is covered by the third TIM layer (see annotated figure above, in a vertical direction the upper surface of 220 is covered by all three TIM layers on the left side).
(Re Claim 27) wherein a surface area of the first TIM layer is greater than a surface area of the second TIM layer and greater than a surface area of the third TIM layer (the first TIM layer may be the bottom layer between 201 and 300 and has a greater area than the next two TIM layers in the stack on the left side, alternatively the recited “a surface area” for each TIM layer may be arbitrarily selected to meet the claimed relationships, a surface area may be ascribed to any portion(s) of the surface area).
(Re Claim 28) further comprising: a first air gap disposed between the first TIM layer and the second TIM layer; and a second air gap disposed between the first TIM layer and the third TIM layer (see annotated figure above, air gaps are present between all of the TIM layers).
(Re Claim 29) wherein a thickness of the first TIM layer, a thickness of the second TIM layer and a thickness of the third TIM layer are substantially the same (see annotated figure above, all thicknesses are substantially the same).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 9, and 30-35 are rejected under 35 U.S.C. 103 as being unpatentable over Casey et al. (US 2010/0181665) in view of Lee et al. (US 2012/0193779), Hung et al. (US 2015/0035134), and Modi et al. (US 2008/0001282).
(Re Claim 1) Casey teaches a semiconductor package structure comprising (e.g. see Fig. 11 and ¶¶ [0028]-[0049]): a first semiconductor die and a second semiconductor die disposed over a substrate, wherein the first semiconductor die includes a first heat output, the second semiconductor die includes a second heat output less than the first heat output; a first thermal interface material (TIM) layer over the first semiconductor die; a second TIM layer over the second semiconductor die; and an underfill between the substrate, the first semiconductor die and the second semiconductor die, wherein a thermal conductivity (Tk) of the first TIM layer is greater than a thermal conductivity of the second TIM layer, an adhesion of the second TIM layer is greater than an adhesion of the first TIM layer, and the first TIM layer is separated from the second TIM layer.
Substrate: 10’; dies: 40’A-40’C; TIM layers: 70’A, 80’, 70’B, underfill 50’A-50’C. Die 40’B is a higher power die having higher heat output, 40’A and 40’C are lower power dies having lower heat output, the TIM materials for the lower power dies have higher adhesion while the TIM materials for the higher power dies have higher thermal conductivity (see ¶¶ [0029], [0031], [0033]-[0034], [0037], [0040]).
Casey is silent regarding wherein the first TIM layer and the second TIM layer are in contact with the underfill. In related art from Lee, additional underfill material 28 may be deposited to fully surround the die and contact the TIM 33 (e.g. see Figs. 8-10). In related art from Modi, additional underfill 16 can be deposited to contact just the edge/corner of a TIM layer 18 (see Fig. 1). In related art from Hung, additional underfill (unlabeled in Fig. 2, between die 12 and substrate 14) can be deposited up to the upper corners/edges of the die and additional TIM 16/16B may be formed to spread over the edges/corners of the die to contact the lateral sides of the underfill. In view of the prior art, a PHOSITA would find such a modification obvious to try to determine if this offers advantages with respect to the processing and/or heat transfer, or other advantages. This would be well within the purview of a skilled artisan as this would only involve depositing slightly more underfill material up to the upper corners/edges of the die (or in the case of Hung, additional TIM material as well). This would be expected to provide additional mechanical integrity and improve heat transfer.
(Re Claim 2) wherein an air gap is formed between the first TIM layer and the second TIM layer to separate the first TIM layer and the second TIM layer from each other (Fig. 11).
(Re Claim 3) further comprising a heat sink (Fig. 11: 20’) over the first TIM layer and the second TIM layer.
(Re Claim 4) wherein the heat sink is in contact with the first TIM layer and the second TIM layer (Fig. 11).
(Re Claim 5) wherein the underfill comprises polymers or fillers.
Casey is silent regarding the material of the underfill. A PHOSITA desiring to make and use Casey’s invention would be motivated to look to related art to teach suitable material of the underfill. In related art from Lee, the underfill is epoxy resin (a polymer) or a silica (filler) and resin combination (¶58). In related art from Modi, the underfill 16 is a polymer (¶19). In view of the prior art, a PHOSITA would find it obvious to select a conventional polymer material for the underfill such as an epoxy resin as this allows the material to be deposited or injected and then cured to provide a strong bond having mechanical integrity.
(Re Claim 9) wherein a thickness of the first TIM layer is substantially the same as a thickness of the second TIM (Fig. 11).
(Re Claim 30) Casey teaches a semiconductor package structure, comprising (e.g. see Fig. 11 and ¶¶ [0028]-[0049]): a first semiconductor die and a second semiconductor die disposed over a substrate along a first direction, wherein the first semiconductor die includes a first heat output and the second semiconductor die includes a second heat output less than the first heat output; a multi-TIM structure disposed over the first semiconductor die and the second semiconductor die, the multi-TIM structure comprises a first TIM layer, a second TIM layer and a third TIM layer, wherein the first TIM layer coves a portion of the first semiconductor die and a portion of the second semiconductor die, the second TIM layer covers another portion of the first semiconductor die, and the third TIM layer covers another portion of the second semiconductor die; and an underfill disposed between the substrate, the first semiconductor die, and the second semiconductor die, wherein a thermal conductivity of the first TIM layer is greater than a thermal conductivity of the second TIM layer and greater than a thermal conductivity of the third TIM layer, and wherein the first TIM layer, the second TIM layer and the third TIM layer are separated from each other by an air gap.
Substrate: 10’; dies: 40’A-40’C (40’B is first die); TIM layers: 70’A (second or third), 80’ (first), 70’B (the other of third or second), underfill 50’A-50’C. Die 40’B is a higher power die having higher heat output, 40’A and 40’C are lower power dies having lower heat output, the TIM materials for the lower power dies have higher adhesion while the TIM materials for the higher power dies have higher thermal conductivity (see ¶¶ [0029], [0031], [0033]-[0034], [0037], [0040]). Regarding “covers” with respect to the first TIM and second die, second TIM and first die, and third TIM and second die: this is met when viewed from the right or left side, at a slight incline, noting “covers” does not require contact or a particular direction or orientation.
Casey is silent regarding wherein the first TIM layer, the second TIM layer and the third TIM layer are in contact with the underfill. In related art from Lee, additional underfill material 28 may be deposited to fully surround the die and contact the TIM 33 (e.g. see Figs. 8-10). In related art from Modi, additional underfill 16 can be deposited to contact just the edge/corner of a TIM layer 18 (see Fig. 1). In related art from Hung, additional underfill (unlabeled in Fig. 2, between die 12 and substrate 14) can be deposited up to the upper corners/edges of the die and additional TIM 16/16B may be formed to spread over the edges/corners of the die to contact the lateral sides of the underfill. In view of the prior art, a PHOSITA would find such a modification obvious to try to determine if this offers advantages with respect to the processing and/or heat transfer, or other advantages. This would be well within the purview of a skilled artisan as this would only involve depositing slightly more underfill material up to the upper corners/edges of the die (or in the case of Hung, additional TIM material as well). This would be expected to provide additional mechanical integrity and improve heat transfer.
(Re Claim 31) further comprising a heat sink (20’) over the multi-TIM structure.
(Re Claim 32) wherein the underfill comprises polymer or fillers.
Casey is silent regarding the material of the underfill. A PHOSITA desiring to make and use Casey’s invention would be motivated to look to related art to teach suitable material of the underfill. In related art from Lee, the underfill is epoxy resin (a polymer) or a silica (filler) and resin combination (¶58). In related art from Modi, the underfill 16 is a polymer (¶19). In view of the prior art, a PHOSITA would find it obvious to select a conventional polymer material for the underfill such as an epoxy resin as this allows the material to be deposited or injected and then cured to provide a strong bond having mechanical integrity.
(Re Claim 33) wherein a thickness of the first TIM layer, a thickness of the second TIM layer and a thickness of the third TIM layer are substantially the same (Fig. 11).
(Re Claim 34) wherein the first TIM layer, the second TIM layer and the third TIM layer are arranged along a second direction parallel with the first direction (Fig. 11).
(Re Claim 35) wherein an area of the first TIM layer is greater than an area of the second TIM layer and greater than an area of the third TIM layer (as recited “a surface area” for each TIM layer may be arbitrarily selected to meet the claimed relationships, a surface area may be ascribed to any portion(s) of the surface area).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional cited art teaches related package structures with TIM layers, underfills, heat sinks, and multiple dies.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK T. K. PETERSON whose telephone number is (571)272-3997. The examiner can normally be reached M-F, 9-5 pm (CST).
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/ERIK T. K. PETERSON/Primary Examiner, Art Unit 2898
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