DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 12, 17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 16 of U.S. Patent No. 12080603 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because:
Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 18 of U.S. Patent No. 12080603 in view of Pranatharthiharan et al. (US 2017/0133459 A1).
Regarding claim 1, claim 16 of US 12080603 B2 teaches a method, comprising:
forming a stack over a substrate (claim 16 of US 12080603 B2 lines 15-16);
depositing a first hard mask layer over the stack (claim 16 of US 12080603 B2 lines 16-17);
depositing a second hard mask layer over the first hard mask layer (claim 16 of US 12080603 B2 lines 18-19);
depositing a third hard mask layer over the second hard mask layer (claim 16 of US 12080603 B2 lines 19-20);
patterning the first hard mask layer, the second hard mask layer, the third hard mask layer, the stack, and the substrate into a plurality of fin-shaped structures (this is implied in lines 15-16 of claim 16 of US 12080603 B2);
forming a patterned masking layer over the plurality of fin-shaped structures, the patterned masking layer including a window to expose a portion of the plurality of fin-shaped structures (claim 16 of US 12080603 B2 lines 22-23);
performing a first etch process to etch the third hard mask layer through the window (claim 16 of US 12080603 B2 lines 27-29);
after the first etch process, performing a second etch process to etch the second hard mask layer through the window (claim 16 of US 12080603 B2 lines 32-34);
after the second etch process, performing a third etch process to substantially remove the second hard mask layer exposed through the window (claim 16 of US 12080603 B2 lines 34-37); and
after the third etch process, etching the portion of the plurality of fin-shaped structures to separate at least one of the plurality of fin-shaped structures into a first segment and a second segment (claim 16 of US 12080603 B2 lines 38-41),
wherein a first thickness of the first hard mask layer is smaller than a second thickness of the second hard mask layer (claim 18 of US 12080603 B2 lines 53-54),
wherein the second thickness of the second hard mask layer is smaller than a third thickness of the third hard mask layer (claim 18 of US 12080603 B2 lines 51-52).
But claim 1 of US 12080603 B2 lines does not teach that the stack comprising a plurality of silicon layers interleaved by a plurality of silicon germanium layers.
Pranatharthiharan teaches a method of forming a nanowire device. The method comprises: forming a stack of alternating layers (12-14 in Fig. 1B of Pranatharthiharan), the stack including a plurality of silicon layers (12) interleaved by a plurality of silicon germanium layers (14); patterning the stack of alternating layers to form fin structures (see Fig. 2B).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have used silicon and silicon germanium layers in the stack in US 12080603 B2 because these are common material choices for nanowire channel materials.
Claim 12 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 17 of U.S. Patent No. 12080603 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because:
Regarding claim 12, claim 16 of US 12080603 B2 teaches a method, comprising:
receiving a workpiece including a fin-shaped structure, a first hard mask layer over the fin-shaped structure, a second hard mask layer over the first hard mask layer and a third hard mask layer over the second hard mask layer (claim 16 of US 12080603 B2 lines 15-20);
forming a patterned masking layer over the workpiece, the patterned masking layer including a mask portion and a window portion, wherein a thickness of the mask portion is greater than a thickness of the window portion such that the third hard mask layer is exposed through the window portion (claim 16 of US 12080603 B2 lines 22-26);
performing a first etch process to etch the exposed third hard mask layer to expose the second hard mask layer through the window portion (claim 16 of US 12080603 B2 lines 26-29);
after the first etch process, performing a second etch process to etch the exposed second hard mask layer, thereby leaving behind second hard mask layer residues (claim 16 of US 12080603 B2 lines 30-34);
after the second etch process, performing a third etch process to remove the second hard mask layer residues and a portion of the patterned masking layer (claim 16 of US 12080603 B2 lines 34-37); and
after the third etch process, etching the fin-shaped structure through the window portion to divide the fin-shaped structure into a first segment and a second segment (claim 16 of US 12080603 B2 lines 38-40),
wherein the first hard mask layer comprises silicon oxide (claim 17 of US 12080603 B2 lines 44),
wherein the second hard mask layer comprises silicon nitride (claim 17 of US 12080603 B2 lines 45-46),
wherein the third hard mask layer comprises silicon oxide (claim 17 of US 12080603 B2 lines 47-48).
Allowable Subject Matter
Claims 1 and 12 would be allowable if rewritten or amended to overcome the double patenting rejection(s) set forth in this Office action.
Claims 2-11, 13-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 17-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 1, the prior art of record does not disclose or fairly suggest a method, comprising: “performing a first etch process to etch the third hard mask layer through the window; after the first etch process, performing a second etch process to etch the second hard mask layer through the window; after the second etch process, performing a third etch process to substantially remove the second hard mask layer exposed through the window;” along with other limitations of the claim.
Regarding claim 12, the prior art of record does not disclose or fairly suggest a method, comprising: “performing a first etch process to etch the exposed third hard mask layer to expose the second hard mask layer through the window portion; after the first etch process, performing a second etch process to etch the exposed second hard mask layer, thereby leaving behind second hard mask layer residues; after the second etch process, performing a third etch process to remove the second hard mask layer residues and a portion of the patterned masking layer” along with other limitations of the claim.
Regarding claim 17, the prior art of record does not disclose or fairly suggest a method, comprising: “performing a first etch process to etch the third hard mask layer through the window; after the first etch process, performing a second etch process to etch the second hard mask layer through the window; after the second etch process, performing a third etch process to substantially remove the second hard mask layer exposed through the window” along with other limitations of the claim.
The prior art of record are Liou et al. (9406521 B1), Chen et al. (US 2018/0226403 A1), Chi et al. (US 2017/0092507 A1).
Liou teaches a method for forming a finFET structure (methods in Figs. 1-7 of Liou). The method includes: patterning a plurality of fin structures using a triple layer mask (141-143 in Figs. 3 of Liou); forming a patterned masking layer (160-200 in Fig. 3), the patterned masking layer has a window region (105 in Fig. 5); etching the fins in the window region to divide the fins into two segments (as shown in Fig. 5-6 of Liou, the etch cuts the fins 120 into two segments). However, Liou does not disclose that the triple-layer hard mask layer is removed layer-by-layer or that it is removed before the fins are cut.
Chen teaches a method of removing a fin structure (Figs. 1-4 of Chen). The method includes: patterning a plurality of fins on a substrate using multilayer hard mask structure (Fig. 1 of Chen); forming a patterned masking layer (28-32 in Fig. 1 of Chen) with a window region (34); exposing the top of the hard mask structure (Fig. 2 of Chen); removing the hard mask structure (Fig. 3 of Chen); removing the fin (Fig. 4 of Chen). However, Chen does not disclose that the multilayer hard mask structures are removed layer-by-layer.
Chi teaches a method of patterning a plurality of fins (Figs. 1-15 of Chi). The method involves forming a multilayer hard mask structure (102-104 in Fig. 7) on a substrate; patterning to form a plurality of fins; removing the remaining hard mask structure (Figs. 8-10 of Chi). However, Chi does not teach the step of etching the fins after removing the hard mask structure. Secondly, Chi does not teach a two-step etching of the second hard mask layer in the multilayer hard mask structure.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN A HOANG whose telephone number is (571)270-0406. The examiner can normally be reached Monday-Friday 8-9am, 10am-6pm EST.
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/Tuan A Hoang/ Primary Examiner, Art Unit 2898
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