DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/11/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 17 is objected to because of the following informalities:
In claim 17, line 5, the limitation of “adjoins” should be corrected into “adjoin”. Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 13-17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3 and 13-17 of U.S. Patent No. 11,757,047. Although the claims at issue are not identical, they are not patentably distinct from each other because the conflicting claims have been patented.
Regarding claim 13, Pat '047 discloses, in claim 1, 3, 5, and 13, a semiconductor structure comprising:
a first dielectric layer; a gate electrode embedded in the first dielectric layer; a gate dielectric layer; a channel layer comprising a semiconducting metal oxide material (all limitations are the same with the limitations recited in claim 1 of Pat '047); and
a source electrode and a drain electrode contacting a top surface of the channel layer ("a source electrode and a drain electrode embedded in the second dielectric layer and contacting a respective portion of a top surface of the channel layer", in claim 1 of Pat '047, is interpreted as the same limitation), wherein:
the channel layer comprises a pair of lengthwise sidewalls that laterally extend along a first horizontal direction and a pair of widthwise sidewalls that laterally extend along a second horizontal direction; the gate electrode has a pair of gate electrode edges that laterally extend along the second horizontal direction and are spaced apart from each other by the width of the gate electrode (all limitations are the same with the limitations recited in claim 3 of Pat '047);
each of the lengthwise sidewalls of the channel layer overlaps with the gate electrode in a plan view ("each lengthwise sidewall selected from the pair of lengthwise sidewalls of the channel layer overlaps with the gate electrode in a plan view", in claim 5 of Pat '047, is interpreted as the same limitation); and
the total length of the periphery of a bottom surface of the channel layer that overlies the gate electrode is equal to twice the width of the gate electrode (all limitations are the same with the limitations recited in claim 5 of Pat '047).
Pat '047 does not explicitly disclose a channel layer disposed on the gate dielectric layer.
Pat '047 teaches, in claim 13, a channel layer disposed on the gate dielectric layer ("a channel layer comprising a semiconducting metal oxide material and located on the gate dielectric layer", in claim 13 of Pat '047, is interpreted as the same limitation), for the purpose of providing bottom gate of a TFT in a precise manner to prevent sidewall re-deposition of metallic materials when patterning the source/drain regions and channel regions of a semiconducting metal oxide TFT device.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in claim 1 of Pat '047 to have the channel layer disposed on the gate dielectric layer, as taught by claim 13 of Pat '047, for the purpose of providing bottom gate of a TFT in a precise manner to prevent sidewall re-deposition of metallic materials when patterning the source/drain regions and channel regions of a semiconducting metal oxide TFT device.
Regarding claim 14, Pat '047 discloses the transistor device of claim 13 as described above.
Pat '047 further teaches, in claim 14, the gate electrode does not overlap with any portion of the pair of widthwise sidewalls of the channel layer in a plan view ("an entire area of the gate electrode does not overlap with any portion of the pair of widthwise sidewalls of the channel layer in a plan view", in claim 14 of Pat '047, is interpreted as the same limitation), for the purpose of providing bottom gate of a TFT in a precise manner to prevent sidewall re-deposition of metallic materials when patterning the source/drain regions and channel regions of a semiconducting metal oxide TFT device.
Regarding claim 15, Pat '047 discloses the transistor device of claim 13 as described above.
Pat '047 further teaches, in claims 13 and 15, a second dielectric layer disposed on the channel layer ("a second dielectric layer embedding a source electrode and a drain electrode and overlying the channel layer ", in claim 13 of Pat '047, is interpreted as the same limitation),
wherein each sidewall of the channel layer is vertically coincident with a respective sidewall of the second dielectric layer (all limitations are the same with the limitations recited in claim 15 of Pat '047), for the purpose of providing bottom gate of a TFT in a precise manner to prevent sidewall re-deposition of metallic materials when patterning the source/drain regions and channel regions of a semiconducting metal oxide TFT device.
Regarding claim 16, Pat '047 discloses the transistor device of claim 15 as described above.
Pat '047 further teaches, in claim 16, a top surface of the source electrode and a top surface of the drain electrode are located within a horizontal plane including a top surface of the second dielectric layer (all limitations are the same with the limitations recited in claim 16 of Pat '047), for the purpose of providing bottom gate of a TFT in a precise manner to prevent sidewall re-deposition of metallic materials when patterning the source/drain regions and channel regions of a semiconducting metal oxide TFT device.
Regarding claim 17, Pat '047 discloses the transistor device of claim 13 as described above.
Pat '047 further teaches, in claim 17, the first dielectric layer comprises a top horizontal surface that contacts the gate dielectric layer and a recessed horizontal surface that does not underlie the gate dielectric layer (all limitations are the same with the limitations recited in claim 17 of Pat '047);
sidewall segments of the first dielectric layer adjoins the top horizontal surface of the first dielectric layer to the recessed horizontal surface of the first dielectric layer; and the sidewall segments of the first dielectric layer and sidewalls of the channel layer are located within a same set of vertical planes ("a set of sidewall segments of the first dielectric layer adjoins the top horizontal surface of the first dielectric layer to the recessed horizontal surface of the first dielectric layer; and the set of sidewall segments of the first dielectric layer and sidewalls of the channel layer are located within a same set of vertical planes", in claim 17 of Pat '047, is interpreted as the same limitation), for the purpose of providing bottom gate of a TFT in a precise manner to prevent sidewall re-deposition of metallic materials when patterning the source/drain regions and channel regions of a semiconducting metal oxide TFT device.
Allowable Subject Matter
Claims 1-12 are allowed because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1 that recite "a first dielectric layer comprising opposing vertical sidewall segments and a recessed horizontal surface that extends horizontally from the vertical sidewall segments" in combination with other elements of the base claims 1.
Claims 18-20 are allowed because the prior art of record neither anticipates nor render obvious the limitations of the base claims 18 that recite "patterning the first dielectric layer, the second dielectric layer, the channel layer, and the gate dielectric layer to form opposing vertical sidewalls that extend into the first dielectric layer" in combination with other elements of the base claims 18.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONG-HO KIM whose telephone number is (571)270-0276. The examiner can normally be reached Monday thru Friday; 8:30 AM to 5PM.
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/TONG-HO KIM/Primary Examiner, Art Unit 2811
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