DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Igarashi et al. (US 2012/0187504) (hereafter Igarashi).
Regarding claim 1, Igarashi discloses a device comprising:
a first transistor (transistor with GE2 in Fig. 32(b)) comprising:
a first semiconductor region (PW2 om Fig. 32(b), paragraph 0083); and
a first gate stack (vertically from GIn to GE2 in Fig. 32(b)) comprising:
a first silicon oxide layer (1s of GIn in Fig. 32(b), paragraph 0150, wherein “SiO.sub.2 film”) over the first semiconductor region (PW2 om Fig. 32(b));
a first hafnium-containing dielectric layer (3n in Fig. 32(b), paragraph 0170, wherein “HfLaON film”) over the first silicon oxide layer (1s of GIn in Fig. 32(b));
a lanthanum-containing dielectric layer 4 (Fig. 32(b), paragraph 0170, wherein “LaO film”) over the first hafnium-containing dielectric layer (3n in Fig. 32(b)); and
a first work-function layer (element number is not shown in Fig. 32(b) but see 11 of GE2 in Fig. 31(b), paragraph 0175, wherein “first metal film 11 for adjusting the work functions of the load transistors LT1 and LT2 is deposited”) over the lanthanum-containing dielectric layer 4 (Fig. 32(b)); and
a second transistor (transistor with GE1 in Fig. 32(a)) comprising:
a second semiconductor region (NW in Fig. 32(a), paragraph 0083); and
a second gate stack (vertically from GIc to GE1 in Fig. 32(a)) comprising:
a second silicon oxide layer (1s of GIc in Fig. 32(a), paragraph 0150, wherein “SiO.sub.2 film”) over the second semiconductor region (NW in Fig. 32(a));
a second hafnium-containing dielectric layer 3 (Fig. 32(a), paragraph 0177, wherein “HfON film”) over the second silicon oxide layer (1s of GIc in Fig. 32(a)); and
a second work-function layer (element number is not shown in Fig. 32(a) but see 11 of GE1 in Fig. 31(a), paragraph 0175, wherein “first metal film 11 for adjusting the work functions of the load transistors LT1 and LT2 is deposited”) over the second hafnium-containing dielectric layer 3 (Fig. 32(a)).
Regarding claim 2, Igarashi further discloses the device of claim 1, wherein the second transistor (transistor with GE1 in Fig. 32(a)) is free from lanthanum (see Figs. 31(a) and 31(b), wherein the lanthanum-containing dielectric layer 4 (Fig. 31(b)) is not formed in Fig. 31(a)) therein.
Regarding claim 3, Igarashi further discloses the device of claim 2, wherein the second gate stack (transistor with GE1 in Fig. 32(a)) is free from lanthanum layer (see Figs. 31(a) and 31(b), wherein the lanthanum-containing dielectric layer 4 (Fig. 31(b)) is not formed in Fig. 31(a)) therein.
Regarding claim 10, Igarashi further discloses the device of claim 1, wherein the first transistor (transistor with GE2 in Fig. 32(b) having NIR) is an n-type transistor, and the second transistor (transistor with GE1 in Fig. 32(a) having PIR) is a p-type transistor.
3. Claims 11 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Son et al. (US 2016/0315164) (hereafter Son).
Regarding claim 11, Son discloses a device comprising:
an n-type transistor (transistor with 320 in Fig. 22, paragraph 0187, wherein “NMOS”) comprising:
a first silicon fin (F2 in Fig. 22, paragraph 0187);
a first silicon oxide layer (321 of 320 in Fig. 22, paragraph 0168; and see paragraph 0074, wherein “silicon oxide SiO.sub.2”) on a top surface and sidewalls of the first silicon fin (see Fig. 16B);
a first high-k dielectric layer (323 and 325 of 320 in Fig. 22, paragraph 0168) over the first silicon oxide layer (321 of 320 in Fig. 22,), wherein the first high-k dielectric layer (323 and 325 of 320 in Fig. 22) comprises hafnium (see paragraph 0009, wherein “a hafnium (Hf)-based material or a zirconium (Zr)-based material”) and lanthanum (see paragraph 0211, wherein “LaOx”); and
a first work function layer (327 of 320 in Fig. 22, paragraph 0174; and see paragraph “work function of the first metal layer”) over the first high-k dielectric layer (323 and 325 of 320 in Fig. 22); and
a p-type transistor (transistor with 320f in Fig. 22, paragraph 0187, wherein “PMOS”) comprising:
a second silicon fin (F1 in Fig. 22, paragraph 0187);
a second silicon oxide layer (321 of 320f in Fig. 22, paragraph 0168; and see paragraph 0074, wherein “silicon oxide SiO.sub.2”) on a top surface and sidewalls of the second silicon fin (see Fig. 16B); and
a second high-k dielectric layer (323 of 320f in Fig. 22, paragraph 0168) over the second silicon oxide layer (321 of 320f in Fig. 22), wherein the second high-k dielectric layer (see paragraph 0009, wherein “a hafnium (Hf)-based material or a zirconium (Zr)-based material”) is free from lanthanum.
Regarding claim 12, Son further discloses the device of claim 11, wherein the first high-k dielectric layer (323 and 325 of 320 in Fig. 22) comprises a hafnium-containing dielectric layer (323 of 320 in Fig. 22; and see paragraph 0009, wherein “a hafnium (Hf)-based material or a zirconium (Zr)-based material”) and a lanthanum-containing dielectric layer (325 of 320 in Fig. 22; and see paragraph 0211, wherein “LaOx”) in contact with each other.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Igarashi as applied to claim 1 above, and further in view of Bohr (US 2016/0247727) (hereafter Bohr).
Regarding claim 4, Igarashi discloses the device of claim 1, however Igarashi does not disclose the first work-function layer comprises titanium and aluminum.
Bohr discloses the first work-function layer 161 (Fig. 8, paragraph 0046; and see paragraph 0041, wherein “hafnium, zirconium, titanium, tantalum, aluminum, their alloys, or carbides of those metals”) comprises titanium and aluminum.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Igarashi to form the first work-function layer comprising titanium and aluminum, as taught by Bohr, since applicant has not disclosed that the claimed material is for a particular unobvious purpose, produces an unexpected result, or is otherwise critical, which are criteria that have been held to be necessary for material limitations to be prima facie unobvious. The claimed material is considered to be a "preferred" or "optimum" material out of a plurality of well known materials that a person of ordinary skill in the art at the time the invention was made would have found obvious to provide to the invention of the cited prior art reference, using routine experimentation and optimization of the invention. In re Leshin, 125 USPQ 416 (CCPA 1960).
Claims 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Igarashi as applied to claim 1 above, and further in view of Nabatame et al. (US 2005/0236675) (hereafter Nabatame).
Regarding claim 5, Igarashi discloses the device of claim 1, however Igarashi does not disclose the first hafnium-containing dielectric layer comprises a hafnium silicate layer and a hafnium oxide layer.
Nabatame discloses the first hafnium-containing dielectric layer 2 (Fig. 2, paragraph 0033) comprises a hafnium silicate layer (vertically from 2s(1) to 2s(13) in Fig. 2, paragraphs 0036-0049) and a hafnium oxide layer (2h(14) in Fig. 2, paragraph 0050).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Igarashi to form the first hafnium-containing dielectric layer comprises a hafnium silicate layer and a hafnium oxide layer, as taught by Nabatame, since a hafnium silicate (HfSiOx) film (Nabatame, paragraph 0004) that enables to decrease Equivalent Oxide Thickness (EOT) of the gate insulating film and enables to increase physical thickness and thereby suppress a gate leak current.
Regarding claim 6, Igarashi in view of Nabatame discloses the device of claim 5, however Igarashi does not disclose the hafnium oxide layer is over the hafnium silicate layer.
Nabatame discloses the hafnium oxide layer (2h(14) in Fig. 2, paragraph 0050) is over the hafnium silicate layer (vertically from 2s(1) to 2s(13) in Fig. 2, paragraphs 0036-0049).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Igarashi to form the hafnium oxide layer being over the hafnium silicate layer, as taught by Nabatame, since a hafnium silicate (HfSiOx) film (Nabatame, paragraph 0004) that enables to decrease Equivalent Oxide Thickness (EOT) of the gate insulating film and enables to increase physical thickness and thereby suppress a gate leak current.
Regarding claim 7, Igarashi in view of Nabatame discloses the device of claim 5, however Igarashi does not disclose the hafnium silicate layer is in contact with both of the hafnium oxide layer and the first silicon oxide layer.
Nabatame discloses the hafnium silicate layer (vertically from 2s(1) to 2s(13) in Fig. 2, paragraphs 0036-0049) is in contact with both of the hafnium oxide layer (2h(14) in Fig. 2, paragraph 0050) and the first silicon oxide layer 2a (Fig. 2, paragraph 0023, wherein “silicon oxide (SiO.sub.2)”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Igarashi to form the hafnium silicate layer being in contact with both of the hafnium oxide layer and the first silicon oxide layer r, as taught by Nabatame, since a hafnium silicate (HfSiOx) film (Nabatame, paragraph 0004) that enables to decrease Equivalent Oxide Thickness (EOT) of the gate insulating film and enables to increase physical thickness and thereby suppress a gate leak current.
Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Igarashi as applied to claim 1 above, and further in view of Maria et al. (US 2001/0032995) (hereafter Maria).
Regarding claim 8, Igarashi discloses the device of claim 1, however Igarashi does not disclose the lanthanum-containing dielectric layer comprises a lanthanum oxide layer and a lanthanum silicon oxide layer contacting the lanthanum oxide layer.
Maria discloses the lanthanum-containing dielectric layer 20’’ (Fig. 4, paragraph 0033) comprises a lanthanum oxide layer 20a (Fig. 4, paragraph 0033) and a lanthanum silicon oxide layer 20b (Fig. 4, paragraph 0033) contacting the lanthanum oxide layer 20a (Fig. 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Igarashi to form the lanthanum-containing dielectric layer comprises a lanthanum oxide layer and a lanthanum silicon oxide layer contacting the lanthanum oxide layer, as taught by Maria, since lanthanum oxide-based gate dielectrics (Maria, paragraph 0007) may be able to provide appropriate chemical reaction resistance and compatibility and/or resistance to crystallization that is desired for highly integrated field effect transistors.
Regarding claim 9, Igarashi in view of Maria discloses the device of claim 8, however Igarashi does not disclose the lanthanum silicon oxide layer is over the lanthanum oxide layer.
Maria discloses the lanthanum silicon oxide layer 20b (Fig. 4, paragraph 0033) is over the lanthanum oxide layer 20a (Fig. 4, paragraph 0033).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Igarashi to form the lanthanum silicon oxide layer being over the lanthanum oxide layer, as taught by Maria, since lanthanum oxide-based gate dielectrics (Maria, paragraph 0007) may be able to provide appropriate chemical reaction resistance and compatibility and/or resistance to crystallization that is desired for highly integrated field effect transistors.
Claims 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Son as applied to claim 12 above, and further in view of Nabatame et al. (US 2005/0236675) (hereafter Nabatame).
Regarding claim 13, Son discloses the device of claim 12, however Son does not disclose the hafnium-containing dielectric layer comprises a hafnium silicate layer and a hafnium oxide layer over the hafnium silicate layer.
Nabatame discloses the hafnium-containing dielectric layer 2 (Fig. 2, paragraph 0033) comprises a hafnium silicate layer (vertically from 2s(1) to 2s(13) in Fig. 2, paragraphs 0036-0049) and a hafnium oxide layer (2h(14) in Fig. 2, paragraph 0050) over the hafnium silicate layer (vertically from 2s(1) to 2s(13) in Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Son to form the hafnium-containing dielectric layer comprising a hafnium silicate layer and a hafnium oxide layer over the hafnium silicate layer, as taught by Nabatame, since a hafnium silicate (HfSiOx) film (Nabatame, paragraph 0004) that enables to decrease Equivalent Oxide Thickness (EOT) of the gate insulating film and enables to increase physical thickness and thereby suppress a gate leak current.
Regarding claim 14, Son in view of Nabatame discloses the device of claim 13, however Son does not disclose a first atomic percentage of hafnium in the hafnium silicate layer is lower than a second atomic percentage of silicon in the hafnium silicate layer.
Nabatame discloses a first atomic percentage of hafnium in the hafnium silicate layer (vertically from 2s(1) to 2s(13) in Fig. 2) is lower (see paragraph 0029, wherein “Hf:Si=8:9”) than a second atomic percentage of silicon in the hafnium silicate layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Son to form a first atomic percentage of hafnium in the hafnium silicate layer being lower than a second atomic percentage of silicon in the hafnium silicate layer, as taught by Nabatame, in order to suppress (Nabatame, paragraph 0031) the defects occurring on the interface between the silicon substrate 1 (Nabatame, Fig. 2, paragraph 0031) and the gate insulating film 2 (Nabatame, Fig. 2, paragraph 0031) as described above, it is necessary to form the gate insulating film 2 (Nabatame, Fig. 2, paragraph 0031) controlled so that the component elements of the gate insulating film 2 (Nabatame, Fig. 2, paragraph 0031) has the concentration distributions from the silicon substrate 1 (Nabatame, Fig. 2, paragraph 0031) toward the gate electrode 3 (Nabatame, Fig. 2, paragraph 0031).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Son in view of Nabatame as applied to claim 13 above, and further in view of Inumiya et al. (US 2014/0070290) (hereafter Inumiya).
Regarding claim 15, Son in view of Nabatame discloses the device of claim 13, however Son and Nabatame do not disclose an atomic percentage of hafnium in the hafnium silicate layer is in a range between about 1 percent and about 5 percent.
Inumiya discloses an atomic percentage of hafnium in the hafnium silicate layer 20 (Fig. 5F, paragraph 0054) is in a range (see paragraph 0054, wherein “the number of Si atoms/(the number of Hf atoms+the number of Si atoms) is less than 0.02 or more than 0.05”) between about 1 percent and about 5 percent.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Son in view of Nabatame to form an atomic percentage of hafnium in the hafnium silicate layer is in a range between about 1 percent and about 5 percent, as taught by Inumiya, since it is possible (Inumiya, paragraph 0055) to avoid any wrong memory operation resulting from the polarization of the gate insulating film 20 (Inumiya, Fig. 5F, paragraph 0055) in the inter-adjacent-cell-gate region caused by a leakage electric field.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Son as applied to claim 12 above, and further in view of Maria et al. (US 2001/0032995) (hereafter Maria).
Regarding claim 16, Son discloses the device of claim 12, however Son does not disclose the lanthanum-containing dielectric layer comprises a lanthanum silicon oxide layer and a lanthanum oxide layer over the lanthanum silicon oxide layer.
Maria discloses the lanthanum-containing dielectric layer 20’’ (Fig. 4, paragraph 0033) comprises a lanthanum silicon oxide layer 20a (Fig. 4, paragraph 0033) and a lanthanum oxide layer 20b (Fig. 4, paragraph 0033) over the lanthanum silicon oxide layer 20a (Fig. 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Son to form the lanthanum-containing dielectric layer comprising a lanthanum silicon oxide layer and a lanthanum oxide layer over the lanthanum silicon oxide layer, as taught by Maria, since lanthanum oxide-based gate dielectrics (Maria, paragraph 0007) may be able to provide appropriate chemical reaction resistance and compatibility and/or resistance to crystallization that is desired for highly integrated field effect transistors.
Claims 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Igarashi et al. (US 2012/0187504) (hereafter Igarashi), in view of Nabatame et al. (US 2005/0236675) (hereafter Nabatame).
Regarding claim 17, Igarashi discloses a device comprising:
a semiconductor region (PW2 om Fig. 32(b), paragraph 0083);
a first gate stack (vertically from GIn to GE2 in Fig. 32(b)) comprising:
a gate dielectric (GIn in Fig. 32(b), paragraph 0150) comprising:
a hafnium-containing dielectric layer (3n in Fig. 32(b), paragraph 0170, wherein “HfLaON film”) over the semiconductor region (PW2 om Fig. 32(b)), wherein the hafnium-containing dielectric layer (3n in Fig. 32(b), paragraph 0170, wherein “HfLaON film”) has a peak hafnium concentration at a first level; and
a lanthanum-containing dielectric layer 4 (Fig. 32(b), paragraph 0170, wherein “LaO film”) over the hafnium-containing dielectric layer (3n in Fig. 32(b)); and
a gate electrode (GE2 in Fig. 32(b), paragraph 0085) over the gate dielectric (GIn in Fig. 32(b)); and
a source/drain region (NIR in Fig. 32(b), paragraph 0085) on a side of the first gate stack (GE2 in Fig. 32(b)).
Igarashi does not disclose the lanthanum-containing dielectric layer has a peak lanthanum concentration at a second level higher than the first level.
Nabatame discloses the lanthanum-containing dielectric layer (2h(14) in Fig. 2) has a peak lanthanum concentration at a second level higher than the first level (2h(2) in Fig. 2).
Nabatame discloses the first hafnium-containing dielectric layer 2 (Fig. 2, paragraph 0033) comprises a hafnium silicate layer (vertically from 2s(1) to 2s(13) in Fig. 2, paragraphs 0036-0049) and a hafnium oxide layer (2h(14) in Fig. 2, paragraph 0050).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Igarashi to form the first hafnium-containing dielectric layer comprises a hafnium silicate layer and a hafnium oxide layer, as taught by Nabatame, since a hafnium silicate (HfSiOx) film (Nabatame, paragraph 0004) that enables to decrease Equivalent Oxide Thickness (EOT) of the gate insulating film and enables to increase physical thickness and thereby suppress a gate leak current.
Regarding claim 18, Igarashi further discloses the device of claim 17, wherein the source/drain region (NIR in Fig. 32(b), paragraph 0085) is of n-type.
Regarding claim 19, Igarashi further discloses the device of claim 17 further comprising a second gate stack (vertically from GIc to GE1 in Fig. 32(a)) comprising hafnium oxide 3 (Fig. 32(a), paragraph 0177, wherein “HfON film”), and the second gate stack is not formed in Fig. 31(a)) is free from lanthanum-containing dielectric layers (see Figs. 31(a) and 31(b), wherein the lanthanum-containing dielectric layer 4 (Fig. 31(b)).
Regarding claim 20, Igarashi further discloses the device of claim 19, wherein the first gate stack (transistor with GE2 in Fig. 32(b) having NIR) is comprised in an n-type transistor, and the second gate stack (transistor with GE1 in Fig. 32(a) having PIR) is comprised in a p-type transistor.
Conclusion
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/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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