DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4, 6-7, 10, 14-17 and 19-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Guler et al. (US 2020/0411661 A1; hereafter Guler).
Regarding claim 1, Guler teaches a semiconductor structure (see e.g., integrated circuit structure 100, Figures 1A and 1B), comprising:
an isolation structure (see e.g., isolation region 106, Para [0024], Figure 1A);
a first dielectric feature formed over the isolation structure (see e.g., self-aligned gate endcap (SAGE) structure 120 formed over the isolation layer 106 between regions 170B and 170C, Para [0028], Figure 1A);
first nanostructures and second nanostructure at opposite sides of the first dielectric feature (see e.g., nanowires 107 formed in region 170B and nanowires 107 formed in region 170C, both these regions are on the opposite sides of the SAGE isolation structure 120, Para [0029], Figure 1A);
a gate structure wrapping around the first nanostructures and the second nanostructures; and (see e.g., gate electrode 150 wrapped around the nanowires 107, Para [0028], Figure 1A)
a metal layer formed over the gate structure (see e.g., local interconnect 154 formed over the gate electrode 150, Para [0028], Figure 1A),
wherein a bottom surface of the metal layer is substantially level with a top surface of the first dielectric feature (see e.g., as shown in Figure 1A the bottom surface of the local interconnect 154 is substantially level with the top surface of SAGE isolation structure 120).
Regarding claim 4, Guler, as referred in claim 1, further teaches
further comprising:
third nanostructures (see e.g., nanowires 107 in region 170A, Paras [0028], [0029], Figure 1A), wherein the gate structure wrapping around the third nanostructures (see e.g., gate electrode 150 wrapped around the nanowires 107 in region 170A, Para [0028], Figure 1A);
a second dielectric feature formed over the isolation structure; and (see e.g., SAGE isolation structure 120 between regions 170A and 170B, Paras [0028], [0029], Figure 1A)
a dielectric layer covering the metal layer (see e.g., inter-layer dielectric stacks 169/dielectric plugs 199 covering the local interconnect 154, Para [0033], Figure 1A),
wherein a portion of the metal layer is vertically sandwiched by the dielectric layer and a top surface of the first dielectric feature (see e.g., a portion of the local interconnect 154 is vertically sandwiched by the inter-layer dielectric stacks 169/dielectric plugs 199 and a top surface of the SAGE isolation structure 120 located between regions 170B and 170C, Figure 1A).
Regarding claim 6, Guler, as referred in claim 4, further teaches
wherein the dielectric layer comprises an extending portion extending through the metal layer and in contact with a top surface of the second dielectric feature (see e.g., the inter-layer dielectric stacks 169/dielectric plugs 199 extend through the local interconnect 154 and contact the top surface of the SAGE isolation structure 120 between regions 170A and 170B, Figure 1A).
Regarding claim 7, Guler teaches a semiconductor structure (see e.g., integrated circuit structure 100, Figure 1A), comprising:
a substrate (see e.g., substrate 102, Para [0024], Figure 1A);
nanostructures formed over the substrate (see e.g., nanowires 107 formed over the substrate 102, Paras [0024], [0025], Figure 1A);
a gate structure wrapping around the nanostructures (see e.g., gate electrode 150 wrapped around the nanowires 107, Para [0028], Figure 1A);
a first dielectric feature separating the gate structure into a first portion and a second portion (see e.g., SAGE isolation structure 120 between regions 170B and 170C, Para [0028], Figure 1A); and
a metal layer formed over the gate structure (see e.g., local interconnect 154 formed over the gate electrode 150, Para [0028], Figure 1A),
wherein top surfaces of the first portion and the second portion of the gate structure and a top surface of the first dielectric feature are covered by the metal layer (see e.g., top surfaces of gate electrode 150 in regions 170B and 170C, and a top surface of the SAGE isolation structure 120 between them is covered by the local interconnect structure 154, Figure 1A).
Regarding claim 10, Guler, as referred in claim 7, further teaches
further comprising:
a second dielectric feature formed adjacent to the nanostructures; and (see e.g., SAGE isolation structure 120 formed between nanowires 107 of regions 170A and 170B, Paras [0028], [0029], Figure 1A)
a dielectric layer formed over the metal layer (see e.g., inter-layer dielectric stacks 169/dielectric plugs 199 covering the local interconnect 154, Para [0033], Figure 10A),
wherein the first dielectric feature and the second dielectric feature are formed at opposite sides of the nanostructures (see e.g., SAGE isolation structures 120 divide the nanowires 107 into three regions 170A, 170B and 170C, Figure 1A), and the dielectric layer is in direct contact with a top surface of the second dielectric feature (see e.g., the inter-layer dielectric stacks 169/dielectric plugs 199 is in direct contact with the top surface of the SAGE isolation structure 120 between regions 170A and 170B, Figure 1A).
Regarding claim 14, Guler teaches a semiconductor structure (see e.g., integrated circuit structure 100, Figures 1A and 1B), comprising:
a substrate (see e.g., substrate 102, Para [0024], Figure 1A);
a first fin base structure protruding from the substrate (see e.g., sub-fin regions 105 protruding from the substrate 102 in region 170B, Para [0024], Figure 1A);
first nanostructures formed over the first fin base structure (see e.g., nanowires 107 formed over the sub-fin region 105 in region 170B, Para [0025], Figure 1A);
a gate structure (see e.g., gate electrode 150, Figure 1A) comprising a first portion (see e.g., region 170B, Figure 1A), a second portion (see e.g., region 170C, Figure 1A), and a third portion (see e.g., region 170A, Figure 1A) over the substrate, wherein the first portion of the gate structure wraps around the first nanostructures (see e.g., gate electrode 150 formed over the substrate 102 and is wrapped around the nanowires 107 in region 170B, Para [0028], Figure 1A);
a first dielectric feature sandwiched between the first portion and the second portion of the gate structure (see e.g., SAGE isolation structure 120 between regions 170B and 170C, Figure 1A);
a second dielectric feature sandwiched between the first portion and the third portion of the gate structure (see e.g., SAGE isolation structure 120 between regions 170A and 170B, Figure 1A);
a metal layer formed over the gate structure; and (see e.g., local interconnect 154 formed over the gate electrode 150, Para [0028], Figure 1A)
a dielectric layer formed over the metal layer and separating the metal layer into a first portion and a second portion (see e.g., the inter-layer dielectric stacks 169/dielectric plugs 199 extend through the local interconnect 154 and separate the local interconnect 154 into a first portion and a second portion, Para [0033], Figure 1A),
wherein the first portion of the metal layer continuously extends from the first portion of the gate structure to the second portion of the gate structure (see e.g., the portion of local interconnect 154 continuously extends from region 170B to region 170C, Figure 1A).
Regarding claim 15, Guler, as referred in claim 14, further teaches
wherein the second portion of the metal layer covers the third portion of the gate structure (see e.g., the portion of local interconnect 154 extends over region 170A, Figure 1A).
Regarding claim 16, Guler, as referred in claim 14, further teaches
wherein a top surface of the first dielectric feature is substantially level with a top surface of the second dielectric feature (see e.g., the SAGE isolation structure 120 between regions 170A and 170B and the SAGE isolation structure 120 between regions 170B and 170C have top surface substantially at the same level, Figure 1A).
Regarding claim 17, Guler, as referred in claim 16, further teaches
wherein the top surface of the first dielectric feature is substantially level with a top surface of the gate structure (see e.g., the top surface of the SAGE isolation structure 120 between regions 170B and 170C is substantially level with the top surface of the gate electrode 150, Figure 1A).
Regarding claim 19, Guler, as referred in claim 14, further teaches
further comprising:
a second fin base structure and a third fin base structure protruding from the substrate; and (see e.g., sub-fin regions 105 protruding from the substrate 102 in regions 170A and 170C, Para [0024], Figure 1A)
second nanostructures formed over the second fin base structure and third nanostructures formed over the third fin base structure (see e.g., nanowires 107 formed over the sub-fin regions 105 in regions 170A and 170C, Para [0025], Figure 1A);
wherein the second portion of the gate structure wraps around the second nanostructures, and the third portion of the gate structure wraps around the third nanostructure (see e.g., gate electrode 150 wraps around the nanowires 107 in regions 170A and 170C, Figure 1A).
Regarding claim 20, Guler, as referred in claim 19, further teaches
further comprising:
first source/drain structures connecting the first nanostructures; and (see e.g., source/drain features 104A and 104B corresponding to the nanowires 107 of region 170B, Para [0029], Figures 1A and 1B)
second source/drain structures connecting the second nanostructures (see e.g., source/drain features 104A and 104B corresponding to the nanowires 107 of region 170C, Figures 1A and 1B),
wherein the first dielectric feature is interposed between the first source/drain structures and the second source/drain structures (see e.g., SAGE isolation structure 120 is interposed between the source and drains of regions 170B and 170C, Figures 1A and 1B).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Guler et al. (US 2020/0411661 A1; hereafter Guler) in view of Subramanian et al. (US 2020/0286891 A1; hereafter Subramanian).
Regarding claim 2, Guler, as referred in claim 1, does not explicitly teach
“wherein the first dielectric feature comprises: a bottom portion comprising a dielectric liner and a dielectric fill layer surrounded by the dielectric liner; and an upper portion formed over the bottom portion”.
In a similar field of endeavor Subramanian teaches
wherein the first dielectric feature comprises: a bottom portion comprising a dielectric liner and a dielectric fill layer surrounded by the dielectric liner; and an upper portion formed over the bottom portion (see e.g., narrower SAGE structure includes a bottom portion, including a dielectric liner 308, a dielectric fill 310, and an upper portion including an optional sacrificial cap 314, and a permanent cap 316, Para [0041], Figure 3A).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Subramanian’s teachings of wherein the first dielectric feature comprises: a bottom portion comprising a dielectric liner and a dielectric fill layer surrounded by the dielectric liner; and an upper portion formed over the bottom portion in the device of Guler as a multiplayer SAGE construction provides reliable trench filling and permits the materials of the lower fill and upper cap to be selected for suitable etch selectivity and structural isolation.
Regarding claim 3, Guler, as modified by Subramanian, teaches the limitations of claim 2 as mentioned above. Guler does not explicitly teach
“wherein the upper portion covers a top surface of the dielectric liner and a top surface of the dielectric fill layer”.
In a similar field of endeavor Subramanian teaches
wherein the upper portion covers a top surface of the dielectric liner and a top surface of the dielectric fill layer (see e.g., narrower SAGE structure includes a bottom portion, including a dielectric liner 308, a dielectric fill 310, and an upper portion including a permanent cap 316 (cap 314 is optional). The cap 316 covers a top surface of the dielectric liner 308 and the dielectric fill material 310, Para [0041], Figure 3A).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Subramanian’s teachings of wherein the upper portion covers a top surface of the dielectric liner and a top surface of the dielectric fill layer in the device of Guler as a multiplayer SAGE construction provides reliable trench filling and permits the materials of the lower fill and upper cap to be selected for suitable etch selectivity and structural isolation.
Claims 5, 8, 11-13 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Guler et al. (US 2020/0411661 A1; hereafter Guler) in view of Guler et al. (US 2022/0399333 A1; hereafter Guler 333’).
Regarding claim 5, Guler, as referred in claim 4, does not explicitly teach
“wherein the metal layer is in contact with a top surface of the second dielectric feature”.
In a similar field of endeavor Guler 333’ teaches
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Modified Figure 6, Guler 333’
wherein the metal layer is in contact with a top surface of the second dielectric feature (see e.g., as shown in modified Figure 6, upper portion of the conductive gate fill material 660 extends over and directly contacts the top surface of the gate end cap structure 653, Para [0050]).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively field to implement Guler 333’s teachings of wherein the metal layer is in contact with a top surface of the second dielectric feature in the device of Guler in order to allow select gate portions to remain electrically connected through the metal interconnect while the dielectric filled opening electrically separates other gate portions, thereby reducing unintended gate to gate shorting and providing greater flexibility in gate routing.
Regarding claim 8, Guler, as referred in claim 7, does not explicitly teach
“wherein the first dielectric feature comprises:
a bottom portion; and
an upper portion formed over the bottom portion,
wherein the upper portion and the bottom portion of the first dielectric feature are made of different dielectric materials”.
In a similar field of endeavor Guler 333’ teaches
wherein the first dielectric feature comprises:
a bottom portion; and (see e.g., gate cut landing structures having a lower portion 318 composed of a low-k material, Para [0040], Figure 3E)
an upper portion formed over the bottom portion (see e.g., gate cut landing structures having a higher-k dielectric cap portion 320 such as, silicon nitride cap portion, formed over the bottom portion 318, Para [0040], Figure 3E),
wherein the upper portion and the bottom portion of the first dielectric feature are made of different dielectric materials (see e.g., the lower portion is made of low-k material and the upper portion is made of silicon nitride, Para [0040], Figure 3E).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Guler 333’s teachings of wherein the first dielectric feature comprises: a bottom portion; and an upper portion formed over the bottom portion, wherein the upper portion and the bottom portion of the first dielectric feature are made of different dielectric materials in the device of Guler in order to provide improved electrical isolation between adjacent gate structures.
Regarding claim 11, Guler, as referred in claim 10, does not explicitly teach
“wherein the dielectric layer is in direct contact with a portion of the gate structure”.
In a similar field of endeavor Guler 333’ teaches
wherein the dielectric layer is in direct contact with a portion of the gate structure (see e.g., as shown in modified Figure 6, the dielectric layer includes the dielectric gate plug 664 and the dielectric gate cap layer 662 which is in direct contact with the gate structure which includes the conductive gate layer 658 and the lower portion of conductive gate fill material 660).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively field to implement Guler 333’s teachings of wherein the dielectric layer is in direct contact with a portion of the gate structure in the device of Guler in order to allow select gate portions to remain electrically connected through the metal interconnect while the dielectric filled opening electrically separates other gate portions, thereby reducing unintended gate to gate shorting and providing greater flexibility in gate routing.
Regarding claim 12, Guler, as referred in claim 10, does not explicitly teach
“wherein the dielectric layer has an extending portion interposed between the gate structure and the second dielectric feature”.
In a similar field of endeavor Guler 333’ teaches
wherein the dielectric layer has an extending portion interposed between the gate structure and the second dielectric feature (see e.g., as shown in modified Figure 6, the dielectric layer includes the dielectric gate plug 664 and the dielectric gate cap layer 662 which has an extending portion interposed between the gate structure including the conductive gate layer 658 and the lower portion of the conductive gate fill material 660, and the gate end cap structure 653).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively field to implement Guler 333’s teachings of wherein the dielectric layer has an extending portion interposed between the gate structure and the second dielectric feature in the device of Guler in order to allow select gate portions to remain electrically connected through the metal interconnect while the dielectric filled opening electrically separates other gate portions, thereby reducing unintended gate to gate shorting and providing greater flexibility in gate routing.
Regarding claim 13, Guler, as referred in claim 10, does not explicitly teach
“wherein the second dielectric feature is partially covered by the metal layer”.
In a similar field of endeavor Guler 333’ teaches
wherein the second dielectric feature is partially covered by the metal layer (see e.g., as shown in modified Figure 6, upper portion of the conductive gate fill material 660 extends over and directly contacts the top surface of the gate end cap structure 653, Para [0050]).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively field to implement Guler 333’s teachings of wherein the second dielectric feature is partially covered by the metal layer in the device of Guler in order to allow select gate portions to remain electrically connected through the metal interconnect while the dielectric filled opening electrically separates other gate portions, thereby reducing unintended gate to gate shorting and providing greater flexibility in gate routing.
Regarding claim 18, Guler, as referred in claim 14, does not explicitly teach
further comprising:
“a gate spacer formed on a sidewall of the gate structure and covering the first dielectric feature and the second dielectric feature”.
In a similar field of endeavor Guler 333’ teaches
a gate spacer formed on a sidewall of the gate structure and covering the first dielectric feature and the second dielectric feature (see e.g., the gate spacers 328A overlaps and covers portions of the dielectric features 318/320, Para [0044], Figure 3G).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Guler 333’s teachings of a gate spacer formed on a sidewall of the gate structure and covering the first dielectric feature and the second dielectric feature in the device of Guler in order to provide improved electrical isolation and protection of the gate structures during subsequent fabrication processes.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Guler et al. (US 2020/0411661 A1; hereafter Guler) in view of Guler et al. (US 2022/0399333 A1; hereafter Guler 333’) and further in view of Guler et al (US 2020/0098878 A1; hereafter Guler 878’).
Regarding claim 9, Guler, as modified by Guler 333’, teaches the limitations of claim 8 as mentioned above. Guler does not explicitly teach
“wherein an interface between the upper portion and the bottom portion of the first dielectric feature is higher than a bottom surface of a topmost nanostructure of the nanostructures”.
In reJapikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950) (Claims to a hydraulic power press which read on the prior art except with regard to the position of the starting switch were held unpatentable because shifting the position of the starting switch would not have modified the operation of the device.); In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975) (the particular placement of a contact in a conductivity measuring device was held to be an obvious matter of design choice), MPEP § 2144.04
Applicant has not established positioning the interface higher than a bottom surface of the topmost nanostructure is critical to the operation of the device or produces any unexpected results.
Guler 333’ teaches a dielectric isolation feature having a bottom portion 318 and an upper portion 320 formed over the bottom portion 318. However, Guler 333’ is silent to the position of the interface between portions 318 and 320 relative to a nanostructure.
In a similar field of endeavor Guler 878’ teaches
wherein an interface between the upper portion and the bottom portion of the first dielectric feature is higher than a bottom surface of a topmost nanostructure of the nanostructures (see e.g., isolating SAGE walls 360 includes a lower dielectric portion and an upper hardmask portion formed over the lower dielectric portion. The interface between the isolating SAGE wall 360 and the hardmask is positioned higher than the bottom surface of topmost nanostructure 355, Figure 3).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Guler 878’s teachings of wherein an interface between the upper portion and the bottom portion of the first dielectric feature is higher than a bottom surface of a topmost nanostructure of the nanostructures in the device of Guler as it would have been an obvious matter of design choice, the rearrangement would have predictably led to the claimed structure.
Conclusion
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/FAKEHA SEHAR/ Examiner, Art Unit 2893
/YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893
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