DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the communications dated 07/11/2024.
Claims 1-20 are pending in this application.
Acknowledges
2. Receipt is acknowledged of the following items from the Applicant.
Information Disclosure Statement (IDS) filed on 07/11/2024. The references cited on the PTOL 1449 form have been considered.
Applicant is requested to cite any relevant prior art if being aware on form PTO-1449 in accordance with the guidelines set for in M.P.E.P. 609.
Specification
3. The specification has been checked to the extent necessary to determine the presence of possible minor errors. However, the applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 U.S.C. § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 1-3, 5-14, 16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over BAE et al. (US 2021/0305427) in view of Yang et al. (US 11,721,697).
Regarding claim 1:
BAE discloses a method, comprising:
depositing, over a substrate 902 (Fig. 22A), a stack comprising first semiconductor layers NS interleaved by second semiconductor layers 904;
patterning the stack and a portion of the substrate 902 to form a fin structure (Fig. 23B) that includes a base fin F9 formed from the substrate 902 and a stack portion (904 & NS) formed from the stack;
forming a dummy gate stack DGS9 (Fig. 24A) over a channel region of the fin structure;
recessing a source/drain region (having recess regions R9, Fig. 24A, para. 0090) of the fin structure to form a source/drain trench R9 extending a depth into the base fin;
selectively and partially etching the second semiconductor layers 904 in the stack portion to form inner spacer openings (paras. 0093-0094);
forming inner spacers 928 (Fig. 25A) in the inner spacer openings;
forming a lower source/drain feature (comprising lower portion of source/drain region 930) to interface the base fin F9 (Fig. 26A);
forming an upper source/drain feature (comprising upper portion of source/drain region 930) to interface sidewalls of the first semiconductor layers NS in the stack portion.
removing the dummy gate stack DGS9 (to form gate space GS, Fig. 26A, paras. 0136-0137);
selectively removing the second semiconductor layers 904 in the stack portion to release the first semiconductor layers NS in the stack portion as channel members NSS; and
forming a gate structure 960 to wrap around each of the channel members NSS and engage the base fin F9.
BAE fails to disclose:
forming an isolation feature over the lower source/drain feature.
Yang discloses:
a method comprising forming a stack comprising first semiconductor layers 14 interleaved by second material layers 12 (see Figs. 10-16, and col. 11, lines 24-67);
forming a lower source/drain feature 34;
forming an isolation feature 42 over the lower source/drain feature; and
forming an upper source/drain feature 44 to interface the sidewalls of the first semiconductor layers 14 in the stack portion.
It would have been obvious to one of ordinary skills in the art at the time the invention was made to modify the invention of BAE to further include forming an isolation feature over the lower source/drain feature, as that taught by Yang, in order to obtain a structure comprising multiple stacked transistors with different and/or independent control/accesses (via different source/drain regions), allowing more different and/or independent functions able to be performed by the structure, thereby to increase the performance of the structure.
Regarding claim 2, BAE/Yang discloses the method of claim 1, further comprising: depositing an interlayer dielectric (ILD) layer 944 (Fig. 27A of BAE) or 54 (Fig. 16 of Yang) over the upper source/drain feature.
Regarding claim 3, BAE/Yang discloses the method of claim 2, further comprising: forming a frontside contact CA9 extending through the ILD layer to interface the upper source/drain feature. See Fig. 28 of BAE.
Regarding claim 5, BAE/Yang discloses the method of claim 1, wherein the lower source/drain feature comprises a first type dopant, wherein the upper source/drain feature comprises a second type dopant different from the first type dopant. See col. 15, lines 25-31 of Yang.
Regarding claim 6, BAE/Yang discloses the method of claim 5, wherein the first type dopant comprises an n-type dopant, wherein the second type dopant comprises a p-type dopant. See col. 15, lines 25-31 of Yang.
Regarding claim 7, BAE/Yang discloses the method of claim 1 comprising all claimed limitations as discussed above, except for wherein the forming of the lower source/drain feature comprises use of a cyclic deposition/etch (CDE) process.
However, it would have been obvious to one of ordinary skills in the art at the time the invention was made that using a cyclic deposition/etch (CDE) process to grow source/drain regions is well known in the art for the advantage of high selectivity, low electrical resistance, low defects, etc.
Regarding claim 8, BAE/Yang discloses the method comprising all claimed limitations as discussed above, except for wherein the depth is between about 10 nm and about 40 nm.
However, it has been held that where the only difference between the prior art and the claims was a recitation of relative dimension or depth of the claimed structure, and a structure having the claimed relative dimension/depth would not perform differently than the prior art structure, the claimed structure was not patentably distinct from the prior art structure (MPEP §2144.04). It would have been obvious that a mere change in shape/size/dimension of a component is generally recognized as being within the level of ordinary skill in the art.
It is to be expected that a change in size/dimension/depth would be an unpatentable modification.
Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art...such ranges are termed "critical ranges and the applicant has the burden of proving such criticality. See In re Aller, 220 F.2d 454, 105 USPQ 233,235 (CCPA 1955).
The instant specification contains no disclosure of either the critical nature of the claimed dimension/depth or of any unexpected results arising therefrom. Where patentability is aid to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. (.In re Woodruff, 919 F.2d 1575, 1578 (Fed. Cir. 1990).)
The claimed limitation regarding to the depth therefore does not bear any critical point that would establish patentability, and is/are not sufficient to patentable distinguish over the prior art.
See MPEP §2144.04).
Regarding claim 9, BAE/Yang discloses the method of claim 1, further comprising: etching the lower source/drain feature such that a top surface of the lower source/drain feature is lower than a top surface of the base fin. See fig. 24A of BAE.
Regarding claim 10:
BAE discloses a method, comprising:
forming, over a substrate 902 (Fig. 22A), a fin structure comprising a base fin F9 (Fig. 23B) formed from the substrate 902 and a stack portion (NS & 904) over the base fin F9, the stack portion comprising first semiconductor layers NS interleaved by second semiconductor layers 904;
forming a dummy gate stack DGS9 (Fig. 24A) over a channel region of the fin structure;
recessing a source/drain region (having recess regions R9, Fig. 24A, para. 0090) of the fin structure to form a source/drain trench R9 extending a depth into the base fin F9;
selectively and partially etching the second semiconductor layers 904 in the stack portion to form inner spacer openings (paras. 0093-0094);
forming inner spacers 928 (Fig. 25A) in the inner spacer openings;
forming a lower source/drain feature (comprising lower portion of source/drain region 930) to interface the base fin F9;
forming an upper source/drain feature 930 to interface sidewalls of the first semiconductor layers NS in the stack portion;
removing the dummy gate stack DGS9 (to form gate space GS, Fig. 26A, paras. 0136-0137);
selectively removing the second semiconductor layers 904 in the stack portion to release the first semiconductor layers NS in the stack portion as channel members NSS; and
forming a gate structure 960 to wrap around each of the channel members NSS and engage the base fin F9.
BAE fails to disclose:
forming the lower source/drain feature using a cyclic deposition/etch (CDE) process;
forming an isolation feature over the lower source/drain feature;
wherein the isolation feature comprises silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, or a combination thereof.
Yang discloses:
a method comprising forming a stack comprising first semiconductor layers 14 interleaved by second material layers 12 (see Figs. 10-16, and col. 11, lines 24-67);
forming a lower source/drain feature 34;
forming an isolation feature 42 over the lower source/drain feature 34; and
forming an upper source/drain feature 44 to interface the sidewalls of the first semiconductor layers 14 in the stack portion;
wherein the isolation feature 42 comprises silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, or a combination thereof (see col. 9, lines 27-32).
It would have been obvious to one of ordinary skills in the art at the time the invention was made to modify the invention of BAE to further include forming an isolation feature over the lower source/drain feature, as that taught by Yang, in order to obtain a structure comprising multiple stacked transistors with different and/or independent control/accesses (via different source/drain regions), allowing more different and/or independent functions able to be performed by the structure, thereby to increase the performance of the structure.
BAE/Yang does not specifically disclose:
forming the lower source/drain feature using a cyclic deposition/etch (CDE) process.
However, it would have been obvious to one of ordinary skills in the art at the time the invention was made that using a cyclic deposition/etch (CDE) process to grow source/drain regions is well known in the art for the advantage of high selectivity, low electrical resistance, low defects, etc.
Regarding claim 11, BAE/Yang discloses the method of claim 10, comprising all claimed limitations, as discussed above, except for wherein the isolation comprises a thickness between about 5 nm and about 15 nm.
However, it has been held that where the only difference between the prior art and the claims was a recitation of relative dimension or thickness of the claimed structure, and a structure having the claimed relative dimension/thickness would not perform differently than the prior art structure, the claimed structure was not patentably distinct from the prior art structure (MPEP §2144.04). It would have been obvious that a mere change in dimension/thickness of a component is generally recognized as being within the level of ordinary skill in the art.
It is to be expected that a change in dimension/thickness would be an unpatentable modification.
Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art...such ranges are termed "critical ranges and the applicant has the burden of proving such criticality. See In re Aller, 220 F.2d 454, 105 USPQ 233,235 (CCPA 1955).
The instant specification contains no disclosure of either the critical nature of the claimed dimension/thickness or of any unexpected results arising therefrom. Where patentability is aid to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. (.In re Woodruff, 919 F.2d 1575, 1578 (Fed. Cir. 1990).)
The claimed limitation regarding to the thickness of the isolation therefore does not bear any critical point that would establish patentability, and is/are not sufficient to patentable distinguish over the prior art.
See MPEP §2144.04).
Regarding claims 12-13, BAE/Yang discloses the method of claim 10, wherein the lower source/drain feature comprises a first type dopant, wherein the upper source/drain feature comprises a second type dopant different from the first type dopant. See the rejections of claims 5-6.
Regarding claim 14, BAE/Yang discloses the method of claim 10, further comprising: forming a frontside contact CA9 to interface the upper source/drain feature. See Fig. 28 of BAE.
Regarding claim 16:
BAE discloses a method, comprising:
receiving a semiconductor substrate 902 (Fig. 22A);
forming a stack of first semiconductor layers NS (Fig. 23B) and second semiconductor layers 904 vertically arranged in an interleaving manner over the semiconductor substrate 902, the first semiconductor layers 904 and the second semiconductor layers NS having different material compositions;
forming a gate structure DGS9 (Fig. 2rA) or 960 (Fig. 27A) over the stack;
recessing portions of the stack on both sides of the gate structure to form source/drain trenches (having recess regions R9, Fig. 24A, para. 0090), the source/drain trenches each having a respective bottom portion R9 below a bottom surface of stack (Fig. 25A);
forming inner spacers 928 in gaps between end portions of vertically adjacent second semiconductor layers 904;
forming first source/drain features (comprising lower portion of source/drain region 930, Fig. 26A) in the bottom portions of the source/drain trenches;
forming second source/drain features (comprising upper portion of source/drain region 930) on the lower source/drain features.
BAE fails to disclose:
forming isolation features on top of and covering the first source/drain features.
Yang discloses:
a method comprising forming a stack comprising first semiconductor layers 14 interleaved by second material layers 12 (see Figs. 10-16, and col. 11, lines 24-67);
forming a lower/first source/drain feature 34;
forming an isolation feature 42 on top and covering the lower/first source/drain feature; and
forming an upper/second source/drain feature 44 to interface the sidewalls of the first semiconductor layers 14 in the stack portion.
It would have been obvious to one of ordinary skills in the art at the time the invention was made to modify the invention of BAE to further include forming an isolation feature over the lower source/drain feature, as that taught by Yang, in order to obtain a structure comprising multiple stacked transistors with different and/or independent control/accesses (via different source/drain regions), allowing more different and/or independent functions able to be performed by the structure, thereby to increase the performance of the structure.
Regarding claim 18, BAE/Yang discloses the method of claim 16, wherein the forming of the first source/drain features includes forming with a first dopant, and the forming of the second source/drain features includes forming with a second dopant, wherein the first dopant and the second dopant has opposite conductivity types. See col. 15, lines 25-31 of Yang.
Regarding claim 19, BAE/Yang discloses the method of claim 16, wherein the forming of the second source/drain features include forming the second source/drain features at least partially spaced away from the isolation features. See Fig. 1 of Yang.
Regarding claim 20, BAE/Yang discloses the method of claim 16, wherein:
the recessing exposes sidewall surfaces for the second semiconductor layers (see Fig. 24A of BAE); and
the forming of the first source/drain features include a plurality of depositions and a plurality of etching operations, wherein the plurality of the etching operations are configured to remove any material on the sidewall surfaces of the second semiconductor layers (see the rejection of claim 7)
.
6. Claims 4, 15, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over BAE et al. (US 2021/0305427) in view of Yang et al. (US 11,721,697), and further in view of Lilak et al. (US 2020/0294998)
Regarding claims 4, and 15, BAE/Yang discloses the method of claim 3, comprising all claimed limitations as discussed above, except for further comprising:
forming a backside contact extending through the substrate to interface the lower source/drain feature.
Lilak discloses a method comprising:
forming a backside contact (filling trenches 761 in Fig. 7B; see also paras. 0055-0056) extending through a substrate 112 to interface a lower source/drain feature 124A. See also Fig. 1A.
it would have been obvious to one of ordinary skills in the art at the time the invention was made to modify the invention of BAE/Yang to further comprise a backside contact as that/those taught by Lilak in order to provide more accessed to the obtained structure, allowing better performance of the structure.
Regarding claim 17, BAE/Yang/Lilak discloses the method of claim 16, further comprising: forming an interlayer dielectric (ILD) 944 (Fig. 27A of BAE) or 54 (Fig. 16 of Yang) over the second source/drain features;
replacing a dummy gate stack DGS9 (Fig. 24A of BAE) of the gate structure with a functional gate stack 960 (Fig. 27A);
forming a first silicide layer 982 (Fig. 28 of BAE) on the first source/drain features and first contacts on the first silicide; and
forming a second silicide layer on the exposed backside of the second source/drain features and second contacts on the second silicide (see para. 0056 of Lilak). See also the rejection of claim 4.
Conclusion
7. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the day of this letter. Failure to respond within the period for response will cause the application to become abandoned (see M.P.E.P 710.02(b)).
A shortened time for reply may be extended up to the maximum six-month period (35 U.S.C. 133). An extension of time fee is normally required to be paid if the reply period is extended. The amount of the fee is dependent upon the length of the extension. Extensions of time are generally not available after an application has been allowed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dao H. Nguyen whose telephone number is (571)272-1791. The examiner can normally be reached on Monday-Friday, 9:00 AM – 5:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke, can be reached on (571)272-1657. The fax numbers for all communication(s) is 571-273-8300.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-1633.
/DAO H NGUYEN/Primary Examiner, Art Unit 2818 September 12, 2026
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