DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/11/2024, 2/23/2026 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 8-9 and 11-12 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-4 of U.S. Patent No. 12,068,386. Although the claims at issue are not identical, they are not patentably distinct from each other because the conflicting claims have been patented.
Regarding claim 8, Pat '386 discloses, in claims 1, 2, and 4, a device comprising:
a first transistor comprising:
a first channel region; a first gate dielectric over the first channel region; and a first gate electrode over the first gate dielectric (all limitations are the same with the limitations recited in claim 1 of Pat '386), the first gate electrode comprising a first p-type work function tuning layer and a second p-type work function tuning layer, the first p-type work function tuning layer comprising fluorine and aluminum, the second p-type work function tuning layer having a lower concentration of fluorine and a lower concentration of aluminum than the first p-type work function tuning layer ("the first gate electrode comprising a first p-type work function tuning layer, the first p-type work function tuning layer comprising fluorine and aluminum", “the first gate electrode further comprises: a second p-type work function tuning layer on the first p-type work function tuning layer”, and “the second p-type work function tuning layer is free of fluorine and aluminum”, in claims 1, 2, and 4 of Pat '525, are interpreted as the same limitation); and
a second transistor comprising: a second channel region; a second gate dielectric over the second channel region; and a second gate electrode over the second gate dielectric, the second gate electrode comprising a n-type work function tuning layer (all limitations are the same with the limitations recited in claim 1 of Pat '386).
Regarding claim 9, Pat '386 discloses the device of claim 8 as described above.
Pat '386 further discloses, in claim 2, the second p-type work function tuning layer is over the first p-type work function tuning layer ("a second p-type work function tuning layer on the first p-type work function tuning layer", in claim 2 of Pat '386, is interpreted as the same limitation).
Regarding claim 11, Pat '386 discloses the device of claim 8 as described above.
Pat '386 further discloses, in claim 3, the second p-type work function tuning layer comprises fluorine and aluminum (all limitations are the same with the limitations recited in claim 3 of Pat '386).
Regarding claim 12, Pat '386 discloses the device of claim 8 as described above.
Pat '386 further discloses, in claim 4, the second p-type work function tuning layer is free of fluorine and aluminum (all limitations are the same with the limitations recited in claim 4 of Pat '386).
Claims 14-16 and 18 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 5, and 12 of U.S. Patent No. 11,688,786 in view of Chiang (US 2021/0066136).
Regarding claim 14, Pat '786 discloses, in claim 1, a device comprising:
a first structure; a second structure; a gate dielectric around the first structure and the second structure; and a first p-type work function tuning layer over the gate dielectric, the first p-type work function tuning layer comprising fluorine and aluminum ("a first channel region; a second channel region; and a gate structure around the first channel region and the second channel region, the gate structure comprising: a gate dielectric layer; a first p-type work function metal on the gate dielectric layer, the first p-type work function metal comprising fluorine and aluminum", in claim 1 of Pat '786, is interpreted as the same limitation).
Pat '786 does not explicitly disclose a source/drain region; a first nanostructure adjacent the source/drain region; a second nanostructure adjacent the source/drain region; a gate dielectric around the first nanostructure and the second nanostructure; a first portion of the first p-type work function tuning layer wrapped around the first nanostructure, a second portion of the first p-type work function tuning layer wrapped around the second nanostructure, the first portion of the first p-type work function tuning layer contacting the second portion of the first p-type work function tuning layer in a region between the first nanostructure and the second nanostructure; the fluorine bonded to the aluminum.
Pat '786 teaches, in claim 12, the fluorine bonded to the aluminum ("the fluorine incorporated during the fluorine treatment bonds to the aluminum incorporated during the aluminum treatment", in claim 12 of Pat '786, is interpreted as the same limitation), for the purpose of providing gate structures having a fluorine-treated work function metal (WFM) layer thereby improving device performance.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in claim 1 of Pat '786 to have the fluorine bonded to the aluminum, as taught by claim 12 of Pat '786, for the purpose of providing gate structures having a fluorine-treated work function metal (WFM) layer thereby improving device performance.
Chiang teaches, in at least figures 2Q-1, 2R-1, 2R-2, and related text, the device comprising a source/drain region (132, [31]); a first nanostructure (lowest 122, [37], figures) adjacent the source/drain region (132, [31]); a second nanostructure (next 122 on lowest 122, [37], figures) adjacent the source/drain region (132, [31]); a gate dielectric (140/142, [39]) around the first nanostructure (lowest 122, [37], figures) and the second nanostructure (next 122 on lowest 122, [37], figures); a first portion of the first p-type work function tuning layer (144, [40]) wrapped around the first nanostructure (lowest 122, [37], figures), a second portion of the first p-type work function tuning layer (144, [40]) wrapped around the second nanostructure (next 122 on lowest 122, [37], figures), the first portion of the first p-type work function tuning layer (144, [40]) contacting the second portion of the first p-type work function tuning layer (144, [40]) in a region between the first nanostructure (lowest 122, [37], figures) and the second nanostructure (next 122 on lowest 122, [37], figures), for the purpose of achieving high Vt in the p-type device region, better Vt control in terms of Vt level and uniformity for semiconductor devices such as FinFET devices with nanowires or nanosheets for multiple GAA structures ([16]).
Pat '786 and Chiang are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '786 with the specified features of Chiang because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '786 to have the source/drain region; the first nanostructure adjacent the source/drain region; the second nanostructure adjacent the source/drain region; the gate dielectric around the first nanostructure and the second nanostructure; the first portion of the first p-type work function tuning layer wrapped around the first nanostructure, the second portion of the first p-type work function tuning layer wrapped around the second nanostructure, the first portion of the first p-type work function tuning layer contacting the second portion of the first p-type work function tuning layer in a region between the first nanostructure and the second nanostructure, as taught by Chiang, for the purpose of achieving high Vt in the p-type device region, better Vt control in terms of Vt level and uniformity for semiconductor devices such as FinFET devices with nanowires or nanosheets for multiple GAA structures ([16], Chiang).
Regarding claim 15, Pat '386 in view of Chiang discloses the device of claim 14 as described above.
Pat '386 further discloses, in claim 1, a fill layer over the first p-type work function tuning layer ("a second p-type work function metal on the first p-type work function metal; a fill layer on the second p-type work function metal", in claim 1 of Pat '786, is interpreted as the same limitation).
Regarding claim 16, Pat '386 in view of Chiang discloses the device of claim 15 as described above.
Pat '386 further discloses, in claim 1, a second p-type work function tuning layer between the fill layer and the first p-type work function tuning layer, the second p-type work function tuning layer having a lower concentration of fluorine and aluminum than the first p-type work function tuning layer ("a second p-type work function metal on the first p-type work function metal, the second p-type work function metal having a lower concentration of fluorine and a lower concentration of aluminum than the first p-type work function metal; and a fill layer on the second p-type work function metal", in claim 1 of Pat '786, is interpreted as the same limitation).
Regarding claim 18, Pat '386 in view of Chiang discloses the device of claim 14 as described above.
Pat '386 further discloses, in claim 5, the gate dielectric comprises fluorine ("the gate dielectric layer comprises fluorine and hafnium ", in claim 5 of Pat '786, is interpreted as the same limitation).
Claim 17 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 12 of U.S. Patent No. 11,688,786 in view of Chiang (US 2021/0066136), and further in view of Lee (US 2020/0381432).
Regarding claim 17, Pat '386 in view of Chiang discloses the device of claim 15 as described above.
Pat '386 in view of Chiang does not explicitly disclose the first p-type work function tuning layer extends continuously between the fill layer and the gate dielectric.
Lee teaches, in at least figure 2 and related text, the device comprising the first p-type work function tuning layer (114a, [69]) extends continuously between the fill layer (118b, [70]) and the gate dielectric (108b, [70]), for the purpose of providing an integrated circuit semiconductor device including three-dimensional transistors that are reliably formed ([4]).
Pat '386, Chiang, and Lee are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '386 in view of Chiang with the specified features of Lee because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '386 in view of Chiang to have the first p-type work function tuning layer extending continuously between the fill layer and the gate dielectric, as taught by Lee, for the purpose of providing an integrated circuit semiconductor device including three-dimensional transistors that are reliably formed ([4], Lee).
Allowable Subject Matter
Claims 1-7 are allowed because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1 that recite "a first pocket of the first metal in contact with the first p-type work function tuning layer; a second pocket of a second metal in contact with the first p-type work function tuning layer, the second metal different than the first metal, the second pocket being disconnected from the first pocket" in combination with other elements of the base claims 1.
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 8 and 10 that recite "the first p-type work function tuning layer is over the second p-type work function tuning layer" in combination with other elements of the base claims 8 and 10.
Claim 13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 8 and 13 that recite "an aluminum pocket between the first p-type work function tuning layer and the second p-type work function tuning layer" in combination with other elements of the base claims 8 and 13.
Claims 19-20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 14 and 19 that recite "an aluminum pocket over the first p-type work function tuning layer" in combination with other elements of the base claims 14 and 19.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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/TONG-HO KIM/Primary Examiner, Art Unit 2811
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