DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 10-17 are objected to because of the following informalities:
In claim 10, line 7, substitute “gat” with --gate-- after “the second.”
Claims 11-17 depend from claim 10, so they are objected for the same reason.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 18 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamada (US Pub. 2011/0284935).
Regarding Claim 18, Yamada discloses a method, comprising: forming a gate structure (101, 102, 130, 150) within an interlayer dielectric (ILD) layer 111 (see fig. 2F), the gate structure (101, 102, 130, 150) including: a gate dielectric layer (101, 130) (page 2, paragraphs 22 and 23), a gate electrode 102 (page 2, paragraph 22) disposed on the gate dielectric layer (101, 130) (see fig. 1A), and a first sidewall spacer 104 (page 2, paragraph 25) (see fig. 1B); recessing the first sidewall spacer 104 and the gate dielectric layer 130 (page 2, paragraphs 27 and 28) to form a tapered opening 107 (page 2, paragraph 28) that exposes a sidewall (upper sidewall) of the gate electrode 102 (see fig. 1E); and forming a second sidewall spacer 108a (page 2, paragraphs 29 and 30) over the tapered opening 107 to interface the recessed first sidewall spacer 104, the recessed gate dielectric layer 130 and the gate electrode 102 (see fig. 2A).
Regarding Claim 20, Yamada discloses wherein the second sidewall spacer 108a has a funnel-shaped cross-sectional profile (because the gate electrode 102 has a tapered shape, as shown in Fig. 1A, the upper portion of the second sidewall spacer 108a has a greater width than the lower portion thereof, thereby forming a funnel-shape cross-sectional profile; see fig. 1E).
Allowable Subject Matter
Claim 19 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 19 recites before the recessing, etching back the ILD layer to form a top recess; depositing a hard mask layer over the etched-back ILD layer; and planarizing the hard mask layer until a top surface of the gate structure is exposed.
These features in combination with the other elements of the base claim are neither disclosed nor suggested by the prior art of record.
Claims 1-9 are allowed and claim 10-17 will be allowed after overcoming the objection set forth above.
The following is an examiner’s statement of reasons for allowance:
Claim 1 recites a gate structure disposed over the isolation structure and extending lengthwise along a first direction; wherein each of the first gate spacer and the second gate spacer comprises: a bottom portion interfacing the isolation structure.
Claim 10 recites a first gate structure and a second gate structure disposed over the isolation structure and extending lengthwise along a first direction; wherein each of the first gate spacer and the second gate spacer comprises: a bottom portion interfacing the isolation structure.
These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record.
Claims 2-9 and 11-17 variously depend from claim 1 or 10, so they are allowed or will be allowed for the same reason.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 18-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 16, 19 and 20 of U.S. Patent No. 12,051,628 (hereinafter “Pat-628”). Although the claims at issue are not identical, they are not patentably distinct from each other because Pat-628 discloses all the claimed limitations.
Regarding Claim 18, Pat-628 discloses a method, comprising: forming a gate structure within an interlayer dielectric (ILD) layer (see claim 16), the gate structure including: a gate dielectric layer (see claim 16), a gate electrode disposed on the gate dielectric layer (see claim 16), and a first sidewall spacer (see claim 16); recessing the first sidewall spacer and the gate dielectric layer (see claim 16) to form a tapered opening (the second sidewall spacer has a funnel-shaped cross-sectional profile; see claim 19; which means a tapered opening exists) that exposes a sidewall of the gate electrode (see claim 16); and forming a second sidewall spacer over the tapered opening to interface the recessed first sidewall spacer, the recessed gate dielectric layer and the gate electrode (see claim 16).
Regarding Claim 19, Pat-628 discloses further comprising: before the recessing, etching back the ILD layer to form a top recess (see claim 20); depositing a hard mask layer over the etched-back ILD layer (see claims 16 and 20); and planarizing the hard mask layer until a top surface of the gate structure is exposed (see claim 16).
Regarding Claim 20, Pat-628 discloses wherein the second sidewall spacer has a funnel-shaped cross-sectional profile (see claim 19).
Claims 18 and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 16 and 20 of U.S. Patent No. 11,488,874 (hereinafter “Pat-874”). Although the claims at issue are not identical, they are not patentably distinct from each other because Pat-874 discloses all the claimed limitations.
Regarding Claim 18, Pat-874 discloses a method, comprising: forming a gate structure within an interlayer dielectric (ILD) layer (see claim 16), the gate structure including: a gate dielectric layer (see claim 16), a gate electrode disposed on the gate dielectric layer (see claim 16), and a first sidewall spacer (see claim 16); recessing the first sidewall spacer and the gate dielectric layer (see claim 16) to form a tapered opening (the second sidewall spacer has a top portion wider than a bottom portion of the second sidewall spacer; see claim 20; which means a tapered opening exists) that exposes a sidewall of the gate electrode (see claim 16); and forming a second sidewall spacer over the tapered opening to interface the recessed first sidewall spacer, the recessed gate dielectric layer and the gate electrode (see claim 16).
Regarding Claim 20, Pat-874 discloses wherein the second sidewall spacer has a funnel-shaped cross-sectional profile (the second sidewall spacer has a top portion wider than a bottom portion of the second sidewall spacer after the forming of the second sidewall spacer in the trench; see claim 20; which forms a funnel-shaped spacer).
Conclusion
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/CHEUNG LEE/Primary Examiner, Art Unit 2812 September 14, 2026
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