DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/11/2024 and 02/25/2026 have been considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 2 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation " the plurality of first semiconductor devices" in lines 4-5.
Claim 2 recites the limitation " the plurality of second semiconductor devices" in lines 8-9.
There is insufficient antecedent basis for this limitation in the claim.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 9 and 13 of U.S. Patent No. 11,552,066 in view of Miyazaki (US 7,727,860).
Regarding claim 1 of the pending application, US Patent teaches a method of forming a semiconductor structure (see claim 9’s preamble), comprising:
forming a bonded assembly of a first wafer including a first semiconductor substrate and a second wafer including a second semiconductor substrate (see claim 9, lines 3-5 or col. 21, lines 39-41);
forming an inter-wafer moat trench extending from a backside surface of the second semiconductor substrate into a proximal portion of the first semiconductor substrate at a periphery of the bonded assembly (see col. 21, lines 45-48);
forming a protective material layer in the inter-wafer moat trench and over the backside surface of the second semiconductor substrate (see col. 21, lines 49-52), wherein the protective material layer comprising a cylindrical plug portion (see claim 13); and
performing at least one thinning process to remove a horizontal portion of the protective material layer and second backside portion of the second semiconductor substrate (see col. 53-56).
US Patent does not mention while the cylindrical plug portion forms a substantially straight cylindrical sidewall.
Miyazaki teaches the same field of an endeavor wherein the outer peripheral grinding machine using a round bar like grindstone to form a fine groove that has a shape of cylindrical trench with a substantially straight cylindrical sidewall (refer to sidewall of trench 24 in fig. 2).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include the outer peripheral grinding machine using a round bar like grind stone to form a fine groove that has a shape of cylindrical trench with a substantially cylindrical sidewall as taught by Miyazaki in the US Patent in order to suppressing chipping or delamination upon grinding, which would cause dimples in a terrace portion.
Since the cylindrical trench with a substantially straight cylindrical sidewall, thus it does not affect the sidewall of the cylindrical trench while performing at least one thinning process to remove a horizontal portion of the protective material layer and second backside portion of the second semiconductor substrate.
Claims 2-5 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 9 and 13 of U.S. Patent No. 11,552,066 in view of Miyazaki (US 7,727,860) as applied to claim 1, and further in view of Huang (US 9,748,206).
Regarding claim 2 of the pending application, US Patent and Miyazaki teach all the limitations for the same reasons as set forth above except for a plurality of first metal interconnect structures within first interconnect-level dielectric layers of the first wafer such that the plurality of first metal interconnect structures are electrically connected to the plurality of first semiconductor devices; and forming a plurality of second metal interconnect structures within second interconnect-level dielectric layers of the second wafer such that the plurality of second metal interconnect structures are electrically connected to the plurality of second semiconductor devices.
Huang teaches the same field of endeavor wherein a plurality of first metal interconnect structures (122) within first interconnect-level dielectric layers (124) of the first wafer (100’) such that the plurality of first metal interconnect structures are electrically connected to the plurality of first semiconductor devices (105); and
forming a plurality of second metal interconnect structures (222) within second interconnect-level dielectric layers (224) of the second wafer (200’) such that the plurality of second metal interconnect structures (122) are electrically connected to the plurality of second semiconductor devices (205) (see fig. 1).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include a plurality of first metal interconnect structures within first interconnect-level dielectric layers of the first wafer such that the plurality of first metal interconnect structures are electrically connected to the plurality of first semiconductor devices; and forming a plurality of second metal interconnect structures within second interconnect-level dielectric layers of the second wafer such that the plurality of second metal interconnect structures are electrically connected to the plurality of second semiconductor devices as taught by Huang in the teaching of US Patent and Miyazaki in order to provide a 3D integrated structure.
Regarding claim 3 of the pending application, US Patent, Miyazaki and Huang teach all the limitations for the same reasons as set forth above. Besides, fig. 1 of Huang teaches forming a plurality of first bonding pads (126) within a first pad-level dielectric layer within the first wafer such that the plurality of first bonding pads are electrically connected to the plurality of first metal interconnect structures; and forming a plurality of second bonding pads (226) within a second pad-level dielectric layer within the second wafer such that the plurality of second bonding pads are electrically connected to the plurality of second metal interconnect structures, wherein forming the bonded assembly further comprises electrically bonding the plurality of first bonding pads to the plurality of second bonding pads (see fig. 1).
Regarding claim 4 of the pending application, US Patent, Miyazaki and Huang teach all the limitations for the same reasons as set forth above. Besides, fig. 1 of Huang teaches the bonded assembly further comprises: placing the first wafer and the second wafer in contact with one another such that the plurality of first bonding pads are in contact with the plurality of second bonding pads and first portions of the first pad-level dielectric layer are in contact with second portions of the second pad-level dielectric layer; performing a first annealing process to induce oxide-to-oxide bonding between the first pad-level dielectric layer and the second pad-level dielectric layer; and performing a second annealing process to induce metal-to-metal bonding between the plurality of first bonding pads and the plurality of second bonding pads (see fig. 2E and its text).
Regarding claim 5 of the pending application, US Patent, Miyazaki and Huang teach all the limitations for the same reasons as set forth above. US Patent inherently teach thinning the second semiconductor substrate to a first thickness; and thinning the second semiconductor substrate to a second thickness that is less than the first thickness after removing the peripheral portion of the bonded assembly (NOTE: claim 9 teaches the thinning back side of the second semiconductor substrate which one having ordinary skills in the art to understand the thickness of the second semiconductor substrate is thinner after the thinning step).
Claim 6 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 9 and 13 of U.S. Patent No. 11,552,066 in view of Miyazaki (US 7,727,860), and further in view of Huang (US 9,748,206) as applied to claim 2, and further in view of Matsugai (US 20120211849).
Regarding claim 6 of the pending application, US Patent, Miyazaki and Huang teach all the limitations for the same reasons as set forth above except for dicing a cylindrical remaining portion of the bonded assembly to generate a plurality of singulated semiconductor chips.
Matsugai teaches the same field of endeavor wherein dicing a cylindrical remaining portion of the bonded assembly to generate a plurality of singulated semiconductor chips (see par. 75-76).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include dicing a cylindrical remaining portion of the bonded assembly to generate a plurality of singulated semiconductor chips as taught by Matsugai in the teaching of US Patent, Miyazaki and Huang in order to prevent the chipping in the peripheral region during the dicing process.
Claim 15 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 9 and 13 of U.S. Patent No. 11,552,066 in view of Miyazaki (US 7,727,860) as applied to claim 1, and further in view of Matsugai (US 20120211849).
Regarding claim 15 of the pending application, US Patent teaches a method of forming a semiconductor structure (see claim 9’s preamble), comprising:
forming a bonded assembly of a first wafer including a first semiconductor substrate and a second wafer including a second semiconductor substrate (see claim 9, lines 3-5 or col. 21, lines 39-41),
Miyazaki teaches the same field of an endeavor wherein the outer peripheral grinding machine using a round bar like grindstone to form a fine groove that has a shape of cylindrical trench with a substantially straight cylindrical sidewall (refer to sidewall of trench 24 in fig. 2).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include the outer peripheral grinding machine using a round bar like grind stone to form a fine groove that has a shape of cylindrical trench with a substantially cylindrical sidewall as taught by Miyazaki in the US Patent in order to suppressing chipping or delamination upon grinding, which would cause dimples in a terrace portion.
US Patent’s claim 9 teaches forming a cylindrical encapsulation dielectric layer (refer to the protective layer formed into the trench) over a cylindrical remaining portion of the bonded assembly.
US Patent and Miyazaki do not teach dicing the cylindrical remaining portion of the bonded assembly to generate a plurality of singulated semiconductor chips.
Matsugai teaches the same field of endeavor wherein dicing a cylindrical remaining portion of the bonded assembly to generate a plurality of singulated semiconductor chips (see par. 75-76).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include dicing a cylindrical remaining portion of the bonded assembly to generate a plurality of singulated semiconductor chips as taught by Matsugai in the teaching of US Patent and Miyazaki in order to prevent the chipping in the peripheral region during the dicing process.
Claim 19 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 9 and 13 of U.S. Patent No. 11,552,066 in view of Miyazaki (US 7,727,860), and further in view of Matsugai (US 20120211849) as applied to claim 2, and further in view of Huang (US 9,748,206).
Regarding claim 19 of the pending application, US Patent, Miyazaki and Matsugai teach all the limitations for the same reasons as set forth above except for forming the bonded assembly further comprises: placing the first wafer and the second wafer in contact with one another such that a plurality of first bonding pads are in contact with a plurality of second bonding pads and first portions of a first pad-level dielectric layer are in contact with second portions of a second pad-level dielectric layer; performing a first annealing process to induce oxide-to-oxide bonding between the first pad-level dielectric layer and the second pad-level dielectric layer; and performing a second annealing process to induce metal-to-metal bonding between the plurality of first bonding pads and the plurality of second bonding pads.
Huang teaches the same field of endeavor wherein fig. 1 of Huang teaches forming a plurality of first bonding pads (126) within a first pad-level dielectric layer within the first wafer such that the plurality of first bonding pads are electrically connected to the plurality of first metal interconnect structures; and forming a plurality of second bonding pads (226) within a second pad-level dielectric layer within the second wafer such that the plurality of second bonding pads are electrically connected to the plurality of second metal interconnect structures, wherein forming the bonded assembly further comprises electrically bonding the plurality of first bonding pads to the plurality of second bonding pads (see fig. 1).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include forming the bonded assembly further comprises: placing the first wafer and the second wafer in contact with one another such that a plurality of first bonding pads are in contact with a plurality of second bonding pads and first portions of a first pad-level dielectric layer are in contact with second portions of a second pad-level dielectric layer; performing a first annealing process to induce oxide-to-oxide bonding between the first pad-level dielectric layer and the second pad-level dielectric layer; and performing a second annealing process to induce metal-to-metal bonding between the plurality of first bonding pads and the plurality of second bonding pads as taught by Huang in the combined teaching of US Patent Miyazaki and Matsugai in order to provide a 3D integrated structure.
Allowable Subject Matter
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “forming a cylindrical encapsulation dielectric layer over the cylindrical sidewall of the bonded assembly prior to dicing the cylindrical remaining portion.”
Claims 8-14 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 8, the prior art of record alone or in combination neither teaches nor makes obvious the invention of a method of forming a semiconductor structure, comprising: “wherein the protective material includes a first protective sublayer, a second sublayer, and a third protective material sublayer; and forming an encapsulation dielectric layer over the third protective material sublayer” in combination of all of the limitations of claim 8. Claims 9-14 include all the limitations of claim 8.
Claim 16 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “removing the cylindrical peripheral portion of the bonded assembly further comprises: forming an annular trench extending from a backside surface of the second semiconductor substrate into a proximal portion of the first semiconductor substrate at a periphery of the bonded assembly; and removing a peripheral portion of the bonded assembly located outside the annular trench.” Claims 17 and 18 include all the limitations of claim 16.
Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “dicing a cylindrical remaining portion of the bonded assembly further comprises: dicing along first dicing channels that are parallel to one another and laterally extend along a first horizontal direction, wherein the first dicing channels are located between neighboring pairs of semiconductor dies within a first wafer and between neighboring pairs of semiconductor dies within a second wafer; and dicing along second dicing channels that are parallel to one another and laterally extend along a second horizontal direction that is perpendicular to the first horizontal direction, wherein the second dicing channels are located between neighboring pairs of semiconductor dies within the first wafer and between neighboring pairs of semiconductor dies within the second wafer, wherein each of the plurality of semiconductor chips generated by dicing along the first dicing channels and the second dicing channels includes a first semiconductor die that is a first singulated portion of the first wafer and a second semiconductor die that is a second singulated portion of the second wafer.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Niki Tram Nguyen whose telephone number is (571) 272-5526. The examiner can normally be reached on 6:00am-4:00pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Steven Loke can be reached on (703)872-9306. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NIKI H NGUYEN/ Primary Examiner, Art Unit 2818
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