DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,087,761. Although the claims at issue are not identical, they are not patentably distinct from each other. The patented claims disclose all the claim limitations of the current application. The patented claims disclose an apparatus comprising: a transistor formed on a semiconductor substrate; an inverter having an output coupled to a gate of the transistor; a plurality of passive components formed under the semiconductor substrate in a backside layer, wherein the plurality of passive components comprises a resistor and a capacitor, wherein the resistor and the capacitor are electrically coupled, through a TSV extending through the backside layer, to an input of the inverter.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,728,330. Although the claims at issue are not identical, they are not patentably distinct from each other. The patented claims disclose all the claim limitations of the current application. The patented claims disclose an apparatus comprising: a transistor formed on a semiconductor substrate; an inverter having an output coupled to a gate of the transistor; a plurality of passive components formed under the semiconductor substrate in a backside layer, wherein the plurality of passive components comprises a resistor and a capacitor, wherein the resistor and the capacitor are electrically coupled, through a TSV extending through the backside layer, to an input of the inverter.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 6-7, 15, and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hung et al. Publication No. US 2022/0231010.
Regarding claims 1, 6, Hung discloses an apparatus comprising:
a transistor [Fig. 6A, transistor 607] formed on a semiconductor substrate [Fig. 3B, substrate 303; par. 0029; “FEOL portion of the layer 309 comprises a semiconductor substrate”];
an inverter having an output coupled to a gate of the transistor [Fig. 6A, inverter comprising 613 and 615 having an output coupled to the gate of 607]; and
a plurality of passive components [Fig. 6A, 609, 611; Fig. 3A, passive device] formed under the semiconductor substrate in a backside layer [Fig. 3A, passive device components formed under the substrate (309) in a power delivery network layer 315; par. 0030],
wherein the plurality of passive components comprises a resistor and a capacitor [Fig. 6A, resistor 611 and capacitor 609], wherein the resistor and the capacitor are electrically coupled, through a through-silicon via (TSV) [Fig. 3A, vias 313; par. 0030] extending through the backside layer, to an input of the inverter [par. 0030; “Moreover, the power delivery network in the PDN layer 315 may be connected to the buried interconnect rails of the FEOL layer by way of metal-filled TSVs (Through-Semiconductor Vias) or by way of damascene-type contacts. Moreover, the FEOL and MEOL layer 309 may also include layer interconnect vias 313 configured to route signals from the PDN layer 315 to the BEOL layer 307.”; par. 0032: “As illustrated in FIG. 3A, during an ESD event, an ESD signal 317 may be routed through the PDN layer 315, the FEOL and MEOL layer 309, and the BEOL layer 307 to the ESD array 305 thereby protecting internal integrated circuits and microdevices from an ESD event occurring at the bump pads 319”].
Regarding claim 7, Hung discloses that the trigger network is electrically connected between a high-power supply rail [Fig. 6A, 601] and a low power supply rail [Fig. 6A, 609], and wherein the transistor [Fig. 6A, 607] is connected between the high-power supply rail and a low power supply rail and configured to provide a current path between the high-power supply rail and a low power supply rail during the ESD current [par. 0041].
Regarding claim 15, Hung discloses a method of forming an electrostatic discharge (ESD) protection device comprising:
forming at least one transistor [Fig. 6A, 607] on a semiconductor substrate [Fig. 3B, substrate 303; par. 0029; “FEOL portion of the layer 309 comprises a semiconductor substrate”];
wherein the at least one transistor is configured to clamp an ESD voltage during an ESD event so as to protect an integrated circuit patterned on the semiconductor substrate from the ESD event [par. 0041];
forming an inverter [Fig. 6A, inverter comprising transistors 613, 615] having an output coupled to respective gates of the at least one transistor [output coupled to the gate of 607], wherein the metal interconnects are configured to interconnect the at least one transistor and the integrated circuit [par. 0028];
forming a trigger network comprising of a capacitor connected in series with a resistor [Fig. 6A, resistor 611 in series with capacitor 609],
wherein the trigger network is formed under the semiconductor substrate [Fig. 3A, passive devices resistor and capacitor are formed in layer 315 under the substrate], and
wherein the trigger network is electrically connected between a high-power supply rail [Fig. 6A, 601] and a low power supply rail [Fig. 6A, 603], and
wherein the resistor and the capacitor are electrically coupled to an input of the inverter [as shown in Fig. 6A]; and
forming an electrical coupling, through vias [Fig. 3A, 313], between a first metal structure of the capacitor and the low power supply rail and between a second metal structure of the capacitor and the first terminal of the resistor [par. 0031, 0032].
Regarding claim 20, Hung discloses that a second terminal of the resistor is connected to the high-power supply rail [Fig. 6A, the top terminal of 611 is connected to 601].
Allowable Subject Matter
Claims 2-5, 8-14, and 16-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance of claims 2, 8, and 16: The prior art does not disclose that the backside layer comprises of one or more metal interconnect levels that are separated by one or more dielectric layers. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record.
Conclusion
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DHARTI PATEL
Primary Examiner
Art Unit 2836
/DHARTI H PATEL/Primary Examiner, Art Unit 2838