DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
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Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wada et al. (US Pub. 2003/0174545).
Regarding claim 1, Fig. 4 and Fig. 7 of Wada discloses a DRAM chip, comprising:
a first sustaining voltage generator [30, Fig. 4] producing a first voltage level which [voltage of SAP_P during Active, Fig. 7] is higher than a voltage level of the signal ONE [voltage on BL_H during Active, Fig. 7] utilized in the DRAM chip [paragraphs 0050 and 0052];
a DRAM cell [21, Fig. 4] comprising an access transistor and a storage capacitor [clearly shows in Fig. 4, each cells has a transistor connects to a capacitor, DRAM];
a sense amplifier [22, Fig. 4] coupled to a bit line [BL_T] and a complementary bit line [BL_C], wherein the bit line [BL_T] is coupled to the storage capacitor through the access transistor [clearly shows in memory cell 21];
an equalization circuit [34, Fig. 4] coupled to the bit line [BL_T] and the complementary bit line [BL_C], wherein the equalization circuit couples the bit line and the complementary bit line to a preset reference voltage during an equalization period [paragraph 0066], and the equalization circuit [34] comprises a VBL line [VBLEQ] which is different from the bit line and the complementary bit line; and
a clean up circuit [35] coupled to the VBL line [BL_T] of the equalization circuit [32, paragraph 0042];
wherein the first sustaining voltage generator [30] is electrically coupled to the bit line [BL_T] during a turning-off period of the access transistor [between T2 and T3 in Fig. 7, access transistor is turning off, but transistor 26 still on by signal OD to couple circuit 30 to bit line (BL_T)], and the clean up circuit [35] is activated to mitigate a difference between a voltage of the bit line and a targeted reference voltage during the equalization period [paragraph 0066].
Regarding claim 2, Fig. 4 of Wada discloses a word line [WL_N] coupled to a gate terminal of the access transistor [as shows in cell 21], wherein the word-line is selected to turn on the access transistor for a first period [before T1] and a second period [between T1 and T2] which is after the first period, and the first sustaining voltage generator [30] is electrically coupled to the bit line [BL_T] during the second period [when OD signal is high in Fig. 7].
Regarding claim 3, Fig. 4 of Wada discloses wherein the first sustaining voltage generator [30] is electrically coupled to the sense amplifier [22] during the second period [between T1 and T2], and the first sustaining voltage generator is electrically coupled to the storage capacitor [within cell 21] of the DRAM cell through the sense amplifier [22] and the bit line [BL_T].
Regarding claim 4, Fig. 7 of Wada discloses wherein the first period [before T1] is an access operation period, and the second period [between T1 and T2] is a restore phase period [paragraph 0052].
Regarding claim 5, Fig. 7 of Wada discloses wherein a kicking charge source [voltage source for BL_H] is electrically coupled to the bit line [BL_T] during the access operation period [when OD signal is active in Fig. 7].
Regarding claim 6, Fig. 7 of Wada discloses wherein the first period comprises a first kick period [before T1] and a second kick period [after T1] separate from the first kick period, a kicking charge source [voltage source that connects to BL_H] is coupled to the bit line during the first kick period, or coupled to the bit line during the first kick period and the second kick period.
Regarding claim 7, Fig. 7 of Wada discloses wherein the voltage level of kicking charge source [voltage on BL_H] is smaller than that of the first sustaining voltage generator [voltage on SAP_P].
Regarding claim 8, Fig. 7 of Wada discloses wherein the word-line [WL] is selected to turn on the access transistor [within cell 21 in Fig. 4] for the first period [before T1] and the second period [between T1 and T2] according to a refresh operation.
Regarding claim 9, Fig. 7 of Wada discloses wherein a kicking charge source is electrically coupled to the bit line [BL_H] for a kick period which is prior to the first period [before T0], and the first sustaining voltage generator [30, Fig. 3] is electrically coupled to the bit line for all the second period [between T1 and T2].
Regarding claim 10, Fig. 7 of Wada discloses wherein the second period [between T1 and T2] is at least 20% of the sum of the kick period [between T and T0], the first period [between T0 and T1] and the second period [between T1 and T2].
Regarding claim 11, Fig. 7 of Wada discloses wherein the second period [between T1 and T2] is at least 50% of the sum of the kick period [between T and T0], the first period [between T0 and T1] and the second period [between T1 and T2].
Regarding claim 12, Fig. 7 of Wada discloses wherein the equalization period is after the turning-off period [after T3] of the access transistor, and the clean up circuit is activated during equalization period [when BLEQL and EQLCN are active high after T3] such that the voltage of the bit line is equal to the preset reference voltage after the equalization period [paragraph 0066].
Regarding claim 13, Fig. 7 of Wada discloses wherein the cleanup circuit [35 in Fig. 11] is activated by a clean up pulse [DSC], and a width of the clean up pulse [DSC] is not greater than that of the equalization period [as shows in Fig. 7, they are the same period].
Regarding claim 14, Fig. 7 of Wada discloses wherein the cleanup circuit [35 in Fig. 11] is activated by a clean up pulse [DSC], and a rising edge of the clean up pulse [DSC] is substantially aligned with a rising edge of the equalization period [EQLCN, they are substantially identical].
Regarding claim 15, Fig. 5 of Wada discloses wherein the clean up circuit [35] comprising a switch circuit [42] coupled to the sense amplifier [22] and a predetermined voltage [VSS].
Regarding claim 16, Fig. 4 of Wada discloses wherein the clean up circuit [35] comprising a switch circuit [42] coupled to the equalization circuit [32] and a predetermined voltage [VSS].
Conclusion
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/ANTHAN TRAN/ Primary Examiner, Art Unit 2825