DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/12/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the claimed subject matter of claim 14 must be shown or the feature(s) canceled from the claim(s). For example, claim 14 recites the limitation “wherein a thickness of the first insulating layer is smaller than a thickness of the second insulating layer”, which does not appear to be shown in the Drawings of the current application, because the claimed “second insulation layer” appears to be directed to element 308, which in all of the Drawings has a smaller thickness than any of the insulating layers that could be construed as the claimed “first insulating layer”. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 16 is objected to because of the following informalities:
Claim 16 recites “,;” in line 9 of the claim, which appears to be a typographical error and should be corrected.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8, 10 and 13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “the metallization pattern” in lines 12-13 of the claim, which is indefinite and unclear, because the claim previously introduces both “a first metallization pattern” and “a second metallization pattern”, and thus it is unclear which specific “metallization pattern” element is being referenced in the limitation “the metallization pattern” in lines 12-13 of the claim.
For the purposes of prosecution, the limitation “the metallization pattern” in lines 12-13 of the claim will be interpreted as reference to the previously cited “second metallization pattern”.
Claim 8 recites the limitation “wherein bottom surfaces of the encapsulant, the first via, and the interconnect device are level” in lines 1-2 of the claim, which is indefinite and unclear, because the limitation does not specify what exactly the claimed elements are leveled with.
For the purposes of prosecution, the limitation “wherein bottom surfaces of the encapsulant, the first via, and the interconnect device are level” will be interpreted as wherein bottom surfaces of the encapsulant, the first via, and the interconnect device are leveled with each other/one another.
Claim 10 recites the limitation “wherein top surfaces of the first insulating layer and the first redistribution layer are level” in lines 1-2 of the claim, which is indefinite and unclear, because the limitation does not specify what exactly the claimed elements are leveled with.
For the purposes of prosecution, the limitation “wherein top surfaces of the first insulating layer and the first redistribution layer are level” will be interpreted as wherein top surfaces of the first insulating layer and the first redistribution layer are leveled with each other/one another.
Claim 13 recites the limitation “wherein top surfaces of the conductive connectors and the molding material layer are level” in lines 1-2 of the claim, which is indefinite and unclear, because the limitation does not specify what exactly the claimed elements are leveled with.
For the purposes of prosecution, the limitation “wherein top surfaces of the conductive connectors and the molding material layer are level” will be interpreted as wherein top surfaces of the conductive connectors and the molding material layer are leveled with each other/one another.
Note the dependent claims 2-8 necessarily inherit the indefiniteness of the claims on which they depend.
A. Prior-art rejections based at least in part by Chiang
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-13 and 15-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chiang et al. (US 2020/0243449 A1, hereinafter “Chiang”).
Regarding independent claim 1, Figure 1H of Chiang discloses a device comprising:
a redistribution structure 192 (“redistribution structure”- ¶0026) comprising a first metallization pattern (i.e., “conductive traces… copper”- ¶0026, specifically the conductive traces electrically connected to pillars 170 and not die 130) in a first dielectric layer (i.e., “dielectric layers”- ¶0026);
an interconnect device 130 (“bridge die”- ¶0020) on the first dielectric layer, wherein the interconnect device 130 is separated from the first metallization pattern;
an encapsulant 154 (“encapsulant”- ¶0025) on the first dielectric layer and surrounding the interconnect device 130;
a first via 170 (“conductive pillars”- ¶0020) extending through the encapsulant 154 to the first metallization pattern;
a second metallization pattern 160 (“conductive vias… copper”- ¶0019) on the encapsulant 154, wherein the second metallization pattern 160 is electrically connected to the first via 170 and the interconnect device 130; and
a first semiconductor die 110 (“die”- ¶0015, not including pads 112) and a second semiconductor die 120 (“die”- ¶0015, not including pads 112) connected to the metallization pattern 152/160, wherein the first semiconductor die 110 is electrically coupled to the second semiconductor die 120 through the interconnect device 130 (¶0021).
Regarding claim 2, Figure 1H of Chiang discloses wherein the first metallization pattern extends on a bottom surface of the encapsulant 154 and the second metallization pattern 160 extends on a top surface of the encapsulant 152, since patterns 160 extend on the top surface of encapsulant 152 at a diagonal angle.
Regarding claim 3, Figure 1H of Chiang discloses the device further comprising a second dielectric layer 152 (“passivation layer”- ¶0019) on the encapsulant 154 and surrounding the second metallization pattern 160.
Regarding claim 4, Figure 1H of Chiang discloses the device further comprising connectors 112 (“conductive pads”- ¶0016) on the second metallization pattern 160, wherein the connectors 112 protrude above the second dielectric layer 152, wherein the first semiconductor die 110 and the second semiconductor die 120 are bonded to the connectors 112.
Regarding claim 5, Figure 1H of Chiang discloses wherein the second metallization pattern 160 is electrically connected to the interconnect device 130 by a solder material 132 (“conductive bumps… C4… bumps”- ¶0020).
Regarding claim 6, Figure 1H of Chiang discloses wherein the interconnect device physically 130 contacts a top surface of the first dielectric layer.
Regarding claim 7, Figure 1H of Chiang discloses wherein the first dielectric layer and the encapsulant 154 comprise different materials (¶¶0018, 0025-0026).
Regarding claim 8, Figure 1H of Chiang discloses wherein bottom surfaces of the encapsulant 154, the first via 170, and the interconnect device 130 are level.
Regarding independent claim 9, Figure 1H of Chiang discloses a structure comprising:
a redistribution structure comprising:
a first insulating layer (i.e., “dielectric layers” of 192- ¶0026);
a first redistribution layer (i.e., “conductive traces” of 192- ¶0026) in the first insulating layer;
a first interconnect device 130 (“bridge die”- ¶0020, not including 132) on the first insulating layer;
a plurality of conductive connectors 132 (“conductive bumps”- ¶0020) on a top surface of the first interconnect device 130;
a molding material layer 154 (“encapsulant”- ¶0025) on the first insulating layer and surrounding the first interconnect device 130;
a second insulating layer 152 (“passivation layer”- ¶0019) on the molding material layer 154 and over the first interconnect device 130; and
a second redistribution layer 160 (“conductive vias”- ¶0019) in the second insulating layer 152 and on the plurality of conductive connectors 132; and
a plurality of semiconductor dies 110, 120 (“die”- ¶0015, not including pads 112) on the redistribution structure, wherein the semiconductor dies 110, 120 are connected to the plurality of conductive connectors 132 by the second redistribution layer 160.
Regarding claim 10, Figure 1H of Chiang discloses wherein top surfaces of the first insulating layer and the first redistribution layer are level.
Regarding claim 11, Figure 1H of Chiang discloses the structure further comprising a passive device (i.e., “passive components”- ¶0022) on the first insulating layer.
Regarding claim 12, Figure 1H of Chiang discloses the structure further comprising a plurality of vias 170 (“conductive pillars”- ¶0020) extending through the molding material layer 154 from the first redistribution layer to the second redistribution layer 160.
Regarding claim 13, Figure 1H of Chiang discloses wherein top surfaces of the conductive connectors 132 and the molding material layer 154 are level.
Regarding claim 15, Figure 1H of Chiang discloses wherein the conductive connectors 132 are respectively surrounded by an underfill 180 (“underfill”- ¶0023).
Regarding independent claim 16, Figure 1H of Chiang discloses a package comprising:
an interconnect structure 194 (“conductive terminals”- ¶0029);
a redistribution structure 192 (“redistribution structure”- ¶0026) bonded to the interconnect structure 194;
an interconnect device 130 (“bridge die”- ¶0020) on a top surface of the redistribution structure 192, wherein the interconnect device 130 comprises a first conductive connector 132a (“conductive bumps”- ¶0020) and a second conductive connector 132b (“conductive bumps”- ¶0020);
a first via 170 (“conductive pillars”- ¶0020) on the top surface of the redistribution structure 192;
an encapsulant 154 (“encapsulant”- ¶0025) on the top surface of the redistribution structure 192, wherein the encapsulant 154 separates the interconnect device 130 from the first via 170,;
a metallization pattern 160 (“conductive vias”… copper”- ¶0019) on top surfaces of the interconnect device 130, the first via 170, and the encapsulant 154, since pattern 160 is on the top surface of encapsulant 154 at a diagonal angle;
a first semiconductor die 110 (“die”- ¶0015, not including pads 112) over a top surface of the metallization pattern 160, wherein the first semiconductor die 110 is electrically connected to the first conductive connector 132a; and
a second semiconductor die 120 (“die”- ¶0015, not including pads 112) over the top surface of the metallization pattern 160, wherein the second semiconductor die 120 is electrically connected to the second conductive connector 132b.
Regarding claim 17, Figure 1H of Chiang discloses wherein the first via 170 and the encapsulant 154 have a same thickness.
Regarding claim 18, Figure 1H of Chiang discloses wherein top surfaces of the encapsulant 154, the first via 170, and the first conductive connector 132a are level.
Regarding claim 19, Figure 1H of Chiang discloses wherein the second semiconductor die 120 is electrically coupled to the first semiconductor die 110 through the interconnect device 130 (¶0021).
Regarding claim 20, Figure 1H of Chiang discloses wherein the first semiconductor die 110 and the second semiconductor die 120 overlap the interconnect device 130.
B. Prior-art rejections based at least in part by Chiang (different interpretation)
Claim Rejections - 35 USC § 102
Claims 9 and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chiang (different interpretation).
Regarding independent claim 9, Figure 1H of Chiang discloses a structure comprising:
a redistribution structure comprising:
a first insulating layer (i.e., “dielectric layers” of 192- ¶0026);
a first redistribution layer (i.e., “conductive traces” of 192- ¶0026) in the first insulating layer;
a first interconnect device 130 (“bridge die”- ¶0020, not including 132) on the first insulating layer;
a plurality of conductive connectors 132 (“conductive bumps”- ¶0020) on a top surface of the first interconnect device 130;
a molding material layer 154 (“encapsulant”- ¶0025) on the first insulating layer and surrounding the first interconnect device 130;
a second insulating layer 150/152 (collectively 150 “insulating encapsulant” and 152 “passivation layer”- ¶¶0019, 0025) on the molding material layer 154 and over the first interconnect device 130; and
a second redistribution layer 160 (“conductive vias”- ¶0019) in the second insulating layer 150/152 and on the plurality of conductive connectors 132; and
a plurality of semiconductor dies 110, 120 (“die”- ¶0015, not including pads 112) on the redistribution structure, wherein the semiconductor dies 110, 120 are connected to the plurality of conductive connectors 132 by the second redistribution layer 160.
Regarding claim 14, Figure 1H of Chiang discloses wherein a thickness of the first insulating layer (i.e., which corresponds with the thickness of 192) is smaller than a thickness of the second insulating layer 150/152 (i.e., the collective thickness of 150 and 152).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Shih (US 2018/0102311 A1), which discloses a device comprising an interconnect device connecting a first semiconductor die to a second semiconductor die.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C CHANG whose telephone number is (571)272-6132. The examiner can normally be reached Mon- Fri 12pm-10pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571)-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAY C CHANG/Primary Examiner, Art Unit 2817
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