DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/12/2024, 3/19/2026 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-2, 4-8, 10-11 and 13-16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 5-6 and 8-12 of U.S. Patent No. 11,659,703. Although the claims at issue are not identical, they are not patentably distinct from each other because the conflicting claims have been patented.
Regarding claim 1, Pat '703 discloses, in claim 1, a semiconductor structure, comprising:
a substrate; a first array of transistor cells over the substrate, wherein each of the transistor cells in the first array includes at least two first-type transistors and four second-type transistors, wherein each of the first- type transistors and the second-type transistors includes an active channel in a single semiconductor fin connecting two source/drain regions, wherein the first array of the transistor cells are arranged with a first X-pitch along a first direction and a first Y-pitch along a second direction perpendicular to the first direction; and a second array of transistor cells over the substrate, wherein each of the transistor cells in the second array includes at least two third-type transistors and four fourth-type transistors, wherein each of the third-type transistors includes an active channel in a single semiconductor fin connecting two source/drain regions, wherein each of the fourth-type transistors includes an active channel in multiple semiconductor fins connecting two source/drain regions, wherein the second array of the transistor cells are arranged with a second X-pitch along the first direction and a second Y-pitch along the second direction, wherein a ratio of the second X-pitch to the first X-pitch is within a range of 1.1 to 1.5 ("A semiconductor structure, comprising: a substrate; an array of first SRAM cells over the substrate, wherein each of the first SRAM cells includes two first p-type FinFET transistors and four first n-type FinFET transistors, wherein each of the first p-type FinFET transistors and the first n-type FinFET transistors includes a transistor channel in a single semiconductor fin and two source/drain regions connected by the transistor channel, wherein the array of the first SRAM cells are arranged with a first X-pitch along a first direction and a first Y-pitch along a second direction perpendicular to the first direction; and an array of second SRAM cells over the substrate, wherein each of the second SRAM cells includes two second p-type FinFET transistors and four second n-type FinFET transistors, wherein each of the second p-type FinFET transistors includes a transistor channel in a single semiconductor fin and two source/drain regions connected by the transistor channel, wherein each of the second n-type FinFET transistors includes a transistor channel in multiple semiconductor fins and two source/drain regions connected by the transistor channel, wherein the array of the second SRAM cells are arranged with a second X-pitch along the first direction and a second Y-pitch along the second direction, wherein a ratio of the second X-pitch to the first X-pitch is within a range of 1.1 to 1.5", in claim 1 of Pat '703, is interpreted as the same limitation).
Regarding claim 2, Pat '703 discloses the semiconductor structure of claim 1 as described above.
Pat '703 further discloses, in claim 1, the source/drain regions of the first-type transistors are doped at a first dopant concentration, the source/drain regions of the third-type transistors are doped at a second dopant concentration, and the first dopant concentration is greater than the second dopant concentration ("the source/drain regions of the first p-type FinFET transistors have a higher boron dopant concentration than the source/drain regions of the second p-type FinFET transistors", in claim 1 of Pat '703, is interpreted as the same limitation).
Regarding claim 4, Pat '703 discloses the semiconductor structure of claim 1 as described above.
Pat '703 further discloses, in claim 2, the source/drain regions of the first-type transistors are doped at a first dopant concentration, the first array of transistors cells are electrically connected to write-assist circuits while the second array of transistors cells are not ("write-assist circuitry connected to each of the first SRAM cells, wherein the second SRAM cells are not connected to a write-assist circuitry ", in claim 2 of Pat '703, is interpreted as the same limitation).
Regarding claim 5, Pat '703 discloses the semiconductor structure of claim 1 as described above.
Pat '703 further discloses, in claim 3, first bit lines disposed in a first metal layer and connected to the first array of transistor cells; and second bit lines disposed in the first metal layer and connected to the second array of transistor cells, wherein the first bit lines have a first width, the second bit lines have a second width, and a ratio of the second width to the first width is greater than 1.2 ("first power supply lines, first bit lines, and first inverse bit lines disposed in a first metal layer; first word lines disposed in a second metal layer over the first metal layer, wherein the first power supply lines, the first bit lines, the first inverse bit lines, and the first word lines are connected to the array of the first SRAM cells; second power supply lines, second bit lines, and second inverse bit lines disposed in the first metal layer; and second word lines disposed in the second metal layer, wherein the second power supply lines, the second bit lines, the second inverse bit lines, and the second word lines are connected to the array of the second SRAM cells, wherein the first bit line and the first inverse bit line have a first width, the second bit line and the second inverse bit line have a second width, and a ratio of the second width to the first width is greater than 1.1", in claim 3 of Pat '703, is interpreted as the same limitation).
Regarding claim 6, Pat '703 discloses the semiconductor structure of claim 1 as described above.
Pat '703 further discloses, in claim 5, each of the second-type transistors and fourth-type transistors includes gate electrodes having a work function layer that includes titanium nitride or tungsten nitride, wherein the work function layer is thicker in the second-type transistors than in the fourth-type transistors ("each of the first n-type FinFET transistors includes a first gate electrode having a first work-function metal layer, each of the second n-type FinFET transistors includes a second gate electrode having a second work- function metal layer, wherein the first and the second work-function metal layers include a same material, wherein the first work-function metal layer is thicker than the second work-function metal layer", in claim 5 of Pat '703, is interpreted as the same limitation).
Regarding claim 7, Pat '703 discloses the semiconductor structure of claim 1 as described above.
Pat '703 further discloses, in claims 6 and 7, each of the second-type transistors includes a first gate electrode having a first work-function metal layer, each of the first-type transistors includes a second gate electrode having a second work-function metal layer, wherein the first and the second work-function metal layers include a same material, wherein each of the fourth-type transistors includes a third gate electrode having a third work-function metal layer, each of the third-type transistors includes a fourth gate electrode having a fourth work-function metal layer, wherein the third and the fourth work-function metal layers include different materials ("each of the first n-type FinFET transistors includes a first gate electrode having a first work-function metal layer, each of the first p-type FinFET transistors includes a second gate electrode having a second work-function metal layer, wherein the first and the second work-function metal layers include a same material" and “each of the second n-type FinFET transistors includes a third gate electrode having a third work-function metal layer, each of the second p-type FinFET transistors includes a fourth gate electrode having a fourth work-function metal layer, wherein the third and the fourth work-function metal layers include different materials”, in claims 6 and 7 of Pat '703, are interpreted as the same limitation).
Regarding claim 8, Pat '703 discloses the semiconductor structure of claim 1 as described above.
Pat '703 does not explicitly disclose a ratio of the first X-pitch to the first Y-pitch is smaller than a ratio of the second X-pitch to the second Y-pitch.
Pat '703 teaches, in claim 11, a ratio of the first X-pitch to the first Y-pitch is smaller than a ratio of the second X-pitch to the second Y-pitch ("the first Y-pitch and the second Y-pitch are about the same, a ratio of the first X-pitch to the first Y-pitch is greater than 2, and a ratio of the second X-pitch to the second Y-pitch is greater than 2.5", in claim 11 of Pat '703, is interpreted as the same limitation), for the purpose of providing the HD memory having both lower leakage and power consumption advantages as well as density improvement and the HC memory having wider channel width for high speed application and is provided with low alpha ratio for cell write margin improvements.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in claim 1 of Pat '703 to have the ratio of the first X-pitch to the first Y-pitch being smaller than a ratio of the second X-pitch to the second Y-pitch, as taught by claim 11 of Pat '703, for the purpose of providing the HD memory having both lower leakage and power consumption advantages as well as density improvement and the HC memory having wider channel width for high speed application and is provided with low alpha ratio for cell write margin improvements.
Regarding claim 10, Pat '703 discloses, in claim 9, a semiconductor structure, comprising: a substrate; an array of first transistor cells over the substrate, wherein each of the first transistor cells includes a first inverter having a first pull-up transistor coupled to a first pull-down transistor and a second inverter having a second pull-up transistor coupled to a second pull-down transistor, the first and the second inverters are cross-coupled to form first data storage nodes, each of the first transistor cells further includes first and second pass-gate transistors for accessing the first data storage nodes, wherein the array of the first transistor cells are arranged with a first X-pitch along a first direction and a first Y-pitch along a second direction perpendicular to the first direction; and an array of second transistor cells over the substrate, wherein each of the second transistor cells includes a third inverter having a third pull-up transistor coupled to a third pull-down transistor and a fourth inverter having a fourth pull-up transistor coupled to a fourth pull-down transistor, the third and the fourth inverters are cross-coupled to form second data storage nodes, each of the second transistor cells further includes third and fourth pass-gate transistors for accessing the second data storage nodes, wherein the array of the second transistor cells are arranged with a second X-pitch along the first direction and a second Y-pitch along the second direction, wherein each of the transistors includes a gate electrode wrapping around a stack of semiconductor channels and source/drain regions connected by the semiconductor channels, wherein a ratio of the second X-pitch to the first X-pitch is within a range of 1.1 to 1.5 ("A semiconductor structure, comprising: a substrate; an array of first SRAM cells over the substrate, wherein each of the first SRAM cells includes a first inverter having a first pull-up GAA transistor coupled to a first pull-down GAA transistor and a second inverter having a second pull-up GAA transistor coupled to a second pull-down GAA transistor, the first and the second inverters are cross-coupled to form first data storage nodes, each of the first SRAM cells further includes first and second pass-gate GAA transistors for accessing the first data storage nodes, wherein the array of the first SRAM cells are arranged with a first X-pitch along a first direction and a first Y-pitch along a second direction perpendicular to the first direction; and an array of second SRAM cells over the substrate, wherein each of the second SRAM cells includes a third inverter having a third pull-up GAA transistor coupled to a third pull-down GAA transistor and a fourth inverter having a fourth pull-up GAA transistor coupled to a fourth pull-down GAA transistor, the third and the fourth inverters are cross-coupled to form second data storage nodes, each of the second SRAM cells further includes third and fourth pass-gate GAA transistors for accessing the second data storage nodes, wherein the array of the second SRAM cells are arranged with a second X-pitch along the first direction and a second Y-pitch along the second direction, wherein each of the GAA transistors includes a gate electrode wrapping around a stack of semiconductor channels and source/drain regions connected by the semiconductor channels, wherein a ratio of the second X-pitch to the first X-pitch is within a range of 1.1 to 1.5", in claim 9 of Pat '703, is interpreted as the same limitation).
Regarding claim 11, Pat '703 discloses the semiconductor structure of claim 10 as described above.
Pat '703 further discloses, in claim 9, the source/drain regions of the first and the second pull-up transistors have a higher boron dopant concentration than the source/drain regions of the third and the fourth pull-up transistors ("the source/drain regions of the first and the second pull-up GAA transistors have a higher boron dopant concentration than the source/drain regions of the third and the fourth pull- up GAA transistors ", in claim 9 of Pat '703, is interpreted as the same limitation).
Regarding claim 13, Pat '703 discloses the semiconductor structure of claim 10 as described above.
Pat '703 further discloses, in claim 11, the first Y-pitch and the second Y-pitch are about the same, a ratio of the first X-pitch to the first Y-pitch is greater than 2, and a ratio of the second X-pitch to the second Y-pitch is greater than 2.5 (all limitations are the same with the limitations recited in claim 11 of Pat '703).
Regarding claim 14, Pat '703 discloses the semiconductor structure of claim 10 as described above.
Pat '703 further discloses, in claim 10, the stack of semiconductor channels of the first and the second pull-down transistors have a first channel width, the stack of semiconductor channels of the third and the fourth pull-down transistors have a second channel width, and the second channel width is greater than the first channel width ("the stack of semiconductor channels of the first and the second pull-down GAA transistors have a first channel width, the stack of semiconductor channels of the third and the fourth pull-down GAA transistors have a second channel width, and a ratio of the second channel width to the first channel width is in a range of 1.2 to 5", in claim 10 of Pat '703, is interpreted as the same limitation).
Regarding claim 15, Pat '703 discloses the semiconductor structure of claim 10 as described above.
Pat '703 further discloses, in claim 12, first bit lines disposed in a first metal layer and connected to the array of the first transistor cells; and second bit lines disposed in the first metal layer and connected to the array of the second transistor cells, wherein the first bit lines have a first width, the second bit lines have a second width, and a ratio of the second width to the first width is greater than 1.2 ("first power supply lines, first bit lines, and first inverse bit lines disposed in a first metal layer and connected to the array of the first SRAM cells; and second power supply lines, second bit lines, and second inverse bit lines disposed in the first metal layer and are connected to the array of the second SRAM cells, wherein the first bit line and the first inverse bit line have a first width, the second bit line and the second inverse bit line have a second width, and a ratio of the second width to the first width is greater than 1.1", in claim 12 of Pat '703, is interpreted as the same limitation).
Regarding claim 16, Pat '703 discloses the semiconductor structure of claim 14 as described above.
Pat '703 does not explicitly disclose the first and the second pull-down transistors have a higher threshold voltage than the third and the fourth pull-down transistors.
Pat '703 teaches, in claim 8, the first and the second pull-down transistors have a higher threshold voltage than the third and the fourth pull-down transistors ("the first n-type FinFET transistors have a higher threshold voltage than the second n-type FinFET transistors", in claim 8 of Pat '703, is interpreted as the same limitation), for the purpose of providing the HD memory having both lower leakage and power consumption advantages as well as density improvement and the HC memory having wider channel width for high speed application and is provided with low alpha ratio for cell write margin improvements.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in claim 14 of Pat '703 to have the first and the second pull-down transistors have a higher threshold voltage than the third and the fourth pull-down transistors, as taught by claim 8 of Pat '703, for the purpose of providing the HD memory having both lower leakage and power consumption advantages as well as density improvement and the HC memory having wider channel width for high speed application and is provided with low alpha ratio for cell write margin improvements.
Claims 17-18 and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 17-18 and 20 of U.S. Patent No. 12,082,389. Although the claims at issue are not identical, they are not patentably distinct from each other because the conflicting claims have been patented.
Regarding claim 17, Pat '389 discloses, in claim 17, a method, comprising: providing a structure having a substrate, a high-density transistor area and a high-current transistor area defined over the substrate, first gate electrodes engaging first channel semiconductor layers in the high-density transistor area, and second gate electrodes engaging second channel semiconductor layers in the high-current transistor area; epitaxially growing first source/drain features in the high-density transistor area and connected to the first channel semiconductor layers; epitaxially growing second source/drain features in the high-current transistor area and connected to the second channel semiconductor layers; doping the first and the second source/drain features with a p-type dopant, wherein the doping includes doping an extra dose of the p-type dopant to the first source/drain features compared to the second source/drain features; forming first contacts over the first source/drain features and electrically connected to the first source/drain features; and forming second contacts over the second source/drain features and electrically connected to the second source/drain features ("A method, comprising: providing a structure having a substrate, a high-density SRAM area and a high-current SRAM area defined over the substrate, first gate electrodes engaging first channel semiconductor layers in the high-density SRAM area, and second gate electrodes engaging second channel semiconductor layers in the high-current SRAM area; epitaxially growing first source/drain features in the high-density SRAM area and connected to the first channel semiconductor layers; epitaxially growing second source/drain features in the high-current SRAM area and connected to the second channel semiconductor layers; performing a first doping to the first and the second source/drain features with a same dose of p-type dopants; performing a second doping to the first source/drain features with an extra dose of the p- type dopants than the second source/drain features; forming first contacts over the first source/drain features and electrically connected to the first source/drain features; and forming second contacts over the second source/drain features and electrically connected to the second source/drain features", in claim 17 of Pat '389, is interpreted as the same limitation).
Regarding claim 18, Pat '389 discloses the method of claim 17 as described above.
Pat '389 further discloses, in claim 18, forming a first mask covering the second source/drain features and exposing the first source/drain features; doping the first source/drain features with the extra dose of the p-type dopants through the first mask; and removing the first mask (all limitations are the same with the limitations recited in claim 18 of Pat '389).
Regarding claim 20, Pat '389 discloses the method of claim 17 as described above.
Pat '389 further discloses, in claim 20, etching first contact holes through an interlayer dielectric layer to expose the first source/drain features; and doping the first source/drain features with the extra dose through the first contact holes (all limitations are the same with the limitations recited in claim 20 of Pat '389).
Claims 3, 9 and 12 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 9 and 11 of U.S. Patent No. 11,659,703 in view of claims 3, 6 and 11 of U.S. Patent 12,082,389.
Regarding claim 3, Pat '703 discloses the semiconductor structure of claim 2 as described above.
Pat '703 further discloses, in claim 1, the first-type transistors and the third-type transistors are doped with boron at the first and the second dopant concentrations respectively ("the source/drain regions of the first p-type FinFET transistors have a higher boron dopant concentration than the source/drain regions of the second p-type FinFET transistors", in claim 1 of Pat '703, is interpreted as the same limitation).
Pat '703 does not explicitly disclose the first dopant concentration is 2 to 5 times higher than the second dopant concentration.
Pat '389 teaches, in claim 3, the first dopant concentration is 2 to 5 times higher than the second dopant concentration (all limitations are the same with the limitations recited in claim 3 of Pat '389), for the purpose of providing the HD memory having both lower leakage and power consumption advantages as well as density improvement and the HC memory having wider channel width for high speed application and is provided with low alpha ratio for cell write margin improvements.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in claim 1 of Pat '703 to have the first dopant concentration being 2 to 5 times higher than the second dopant concentration, as taught by claim 3 of Pat '389, for the purpose of providing the HD memory having both lower leakage and power consumption advantages as well as density improvement and the HC memory having wider channel width for high speed application and is provided with low alpha ratio for cell write margin improvements.
Regarding claim 9, Pat '703 discloses the semiconductor structure of claim 8 as described above.
Pat '703 does not explicitly disclose the first Y-pitch and the second Y-pitch are about the same, the ratio of the first X-pitch to the first Y-pitch is in a range of 2 to 2.5, and the ratio of the second X-pitch to the second Y-pitch is in a range of 2.5 to 3.5.
Pat '389 teaches, in claim 6, the first Y-pitch and the second Y-pitch are about the same, the ratio of the first X-pitch to the first Y-pitch is in a range of 2 to 2.5, and the ratio of the second X-pitch to the second Y-pitch is in a range of 2.5 to 3.5 ("a ratio of the first pitch to the second pitch is in a range of 2 to 2.5, and a ratio of the third pitch to the fourth pitch is in a range of 2.5 to 3.5", in claim 6 of Pat '389, is interpreted as the same limitation), for the purpose of providing the HD memory having both lower leakage and power consumption advantages as well as density improvement and the HC memory having wider channel width for high speed application and is provided with low alpha ratio for cell write margin improvements.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in claim 1 of Pat '703 to have the first dopant concentration being 2 to 5 times higher than the second dopant concentration, as taught by claim 3 of Pat '389, for the purpose of providing the HD memory having both lower leakage and power consumption advantages as well as density improvement and the HC memory having wider channel width for high speed application and is provided with low alpha ratio for cell write margin improvements.
Regarding claim 12, Pat '703 discloses the semiconductor structure of claim 11 as described above.
Pat '703 does not explicitly disclose the boron dopant concentration in the source/drain regions of the first and second pull-up transistors is 2 to 5 times higher than the boron dopant concentration in the source/drain regions of the third and fourth pull-up transistors.
Pat '389 teaches, in claim 11, the boron dopant concentration in the source/drain regions of the first and second pull-up transistors is 2 to 5 times higher than the boron dopant concentration in the source/drain regions of the third and fourth pull-up transistors (all limitations are the same with the limitations recited in claim 11 of Pat '389), for the purpose of providing the HD memory having both lower leakage and power consumption advantages as well as density improvement and the HC memory having wider channel width for high speed application and is provided with low alpha ratio for cell write margin improvements.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in claim 1 of Pat '703 to have the boron dopant concentration in the source/drain regions of the first and second pull-up transistors being 2 to 5 times higher than the boron dopant concentration in the source/drain regions of the third and fourth pull-up transistors, as taught by claim 3 of Pat '389, for the purpose of providing the HD memory having both lower leakage and power consumption advantages as well as density improvement and the HC memory having wider channel width for high speed application and is provided with low alpha ratio for cell write margin improvements.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4 and 8-9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liaw (US 2013/0141962).
Regarding claim 1, Liaw discloses, in at least figures 3-6 and related text, a semiconductor structure, comprising:
a substrate (31, [35]);
a first array of transistor cells (50, [36], figure 5) over the substrate (31, [35]), wherein each of the transistor cells in the first array includes at least two first-type transistors (PU-1/PU-2, [36]) and four second-type transistors (PD-1/PD-2/PG-1/PG-2, [36]), wherein each of the first-type transistors (PU-1/PU-2, [36]) and the second-type transistors (PD-1/PD-2/PG-1/PG-2, [36]) includes an active channel in a single semiconductor fin (fin1/fin2/fin3/fin4, [36]) connecting two source/drain regions, wherein the first array of the transistor cells (50, [36], figure 5) are arranged with a first X-pitch along a first direction (horizontal direction, figures) and a first Y-pitch along a second direction (vertical direction, figures) perpendicular to the first direction (horizontal direction, figures) (figures); and
a second array of transistor cells (60, [40], figure 6) over the substrate (31, [35]), wherein each of the transistor cells in the second array includes at least two third-type transistors (PU-1/PU-2, [40]) and four fourth-type transistors (PD-1/PD-2/PG-1/PG-2, [40]), wherein each of the third-type transistors (PU-1/PU-2, [40]) includes an active channel in a single semiconductor fin (fin2/fin3, [40]) connecting two source/drain regions, wherein each of the fourth-type transistors (PD-1/PD-2/PG-1/PG-2, [40]) includes an active channel in multiple semiconductor fins (fin1A/fin1B/fin4A/fin4B, [41]) connecting two source/drain regions, wherein the second array of the transistor cells (60, [40], figure 6) are arranged with a second X-pitch along the first direction (horizontal direction, figures) and a second Y-pitch along the second direction (vertical direction, figures),
wherein a ratio of the second X-pitch to the first X-pitch is within a range of 1.1 to 1.5 ([42]).
Regarding claim 4, Liaw discloses the semiconductor structure of claim 1 as described above.
Liaw further discloses, in at least figures 3-6 and related text, the first array of transistors cells are electrically connected to write-assist circuits while the second array of transistors cells are not ([64], [81]).
Regarding claim 8, Liaw discloses the semiconductor structure of claim 1 as described above.
Liaw further discloses, in at least figures 3-6 and related text, a ratio of the first X-pitch to the first Y-pitch is smaller than a ratio of the second X-pitch to the second Y-pitch ([82]).
Regarding claim 9, Liaw discloses the semiconductor structure of claim 8 as described above.
Liaw further discloses, in at least figures 3-6 and related text, the first Y-pitch and the second Y-pitch are about the same, the ratio of the first X-pitch to the first Y-pitch is in a range of 2 to 2.5, and the ratio of the second X-pitch to the second Y-pitch is in a range of 2.5 to 3.5 ([82]).
Claim(s) 10 and 14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liaw (US 2020/0135740).
Regarding claim 10, Liaw discloses, in at least figures 1-3A and related text, a semiconductor structure, comprising:
a substrate (201, [27]);
an array of first transistor cells (200, [23]) over the substrate (201, [27]), wherein each of the first transistor cells (200, [23]) includes a first inverter having a first pull-up transistor (206, PU-1, [23]) coupled to a first pull-down transistor (210, PD-1, [23]) and a second inverter having a second pull-up transistor (208, PU-2, [23]) coupled to a second pull-down transistor (212, PD-2, [23]), the first and the second inverters are cross-coupled to form first data storage nodes (114, [21]), each of the first transistor cells (200, [23]) further includes first (202, PG-1, [23]) and second (204, PG-2, [23]) pass-gate transistors for accessing the first data storage nodes (114, [21]), wherein the array of the first transistor cells (200, [23]) are arranged with a first X-pitch along a first direction (x direction, figures) and a first Y-pitch along a second direction (y direction, figures) perpendicular to the first direction (x direction, figures); and
an array of second transistor cells (300, [31]) over the substrate (201, [27]), wherein each of the second transistor cells (300, [31]) includes a third inverter having a third pull-up transistor (306, PU-1, [31]) coupled to a third pull-down transistor (310, PD-1, [31]) and a fourth inverter having a fourth pull-up transistor (308, PU-2, [31]) coupled to a fourth pull-down transistor (312, PD-2, [31]), the third and the fourth inverters are cross-coupled to form second data storage nodes (114, [21]), each of the second transistor cells (300, [31]) further includes third (302, PG-1, [31]) and fourth (304, PG-2, [31]) pass-gate transistors for accessing the second data storage nodes (114, [21]), wherein the array of the second transistor cells (300, [31]) are arranged with a second X-pitch along the first direction (x direction, figures) and a second Y-pitch along the second direction (y direction, figures),
wherein each of the transistors includes a gate electrode (230/235/330/335, [27], [35]) wrapping around a stack of semiconductor channels (253/255/353/355, [27], [35]) and source/drain regions (250, [29]) connected by the semiconductor channels (253/255/353/355, [27], [35]),
wherein a ratio of the second X-pitch to the first X-pitch is within a range of 1.1 to 1.5 ([40]).
Regarding claim 14, Liaw discloses the semiconductor structure of claim 10 as described above.
Liaw further discloses, in at least figures 1-3A and related text, the stack of semiconductor channels of the first (255 of 202, [27]) and the second (255 of 212, [27]) pull-down transistors have a first channel width (W1, [27]), the stack of semiconductor channels of the third (355 of 302, [35]) and the fourth (355 of 312, [35]) pull-down transistors have a second channel width (W2, [35]), and the second channel width is greater than the first channel width (figures).
Allowable Subject Matter
Claim 19 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 17 and 19 that recite "the doping of the extra dose is performed before the forming of the interlayer dielectric layer" in combination with other elements of the base claims 17 and 19.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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/TONG-HO KIM/Primary Examiner, Art Unit 2811
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