Prosecution Insights
Last updated: October 01, 2026
Application No. 18/770,906

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE INCLUDING SUPPORTING LAYER

Non-Final OA §102§103
Filed
Jul 12, 2024
Examiner
PHAM, HOAI V
Art Unit
2892
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
NANYA TECHNOLOGY Corporation
OA Round
1 (Non-Final)
89%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
88%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allowance Rate
634 granted / 712 resolved
+21.0% vs TC avg
Minimal -1% lift
Without
With
+-1.2%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
11 currently pending
Career history
720
Total Applications
across all art units

Statute-Specific Performance

§101
1.1%
-38.9% vs TC avg
§103
36.5%
-3.5% vs TC avg
§102
37.4%
-2.6% vs TC avg
§112
14.6%
-25.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 712 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-2 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cho et al [US 2024/0155828]. With respect to claim 1, Cho et al (figs. 10A-10K) disclose a method of manufacturing a semiconductor device, comprising: providing a carrier (110, pp [0101]); forming a lower supporting layer (126p, pp [0108]) having an opening (126H, pp [0108]) over the carrier; forming a first electrode (LE, pp [0110]) within the opening, wherein the first electrode has an upper surface far away from the carrier; forming an upper supporting layer (144P, pp [0109]) abutting the upper surface of the first electrode; and forming a capacitor dielectric (160, pp [0109]) and a second electrode (UE1, pp [0118]) on the first electrode. With respect to claim 2, Cho et al (figs. 10A-10K) disclose further comprising: forming an upper sacrifice layer (134, pp [0104]) on the lower supporting layer (126p, pp [0108]), wherein the upper sacrifice layer and the lower supporting layer collectively define the opening (BH, pp [0106]); and removing a first portion of the upper sacrifice layer (fig. 10E, pp [0112]) to expose a lateral surface of the first electrode (LE, pp [0110]). With respect to claim 7, Cho et al (figs. 10A-10K) disclose further comprising: forming a mask (MP, pp [0106]) on the upper sacrifice layer; and patterning the upper sacrifice layer and the lower supporting layer to form the opening (BH, pp [0106]). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al [US 2024/0155828] in view of Kim et al [US 2005/0176210]. With respect to claim 8, Cho et al fail to disclose wherein forming the first electrode comprises: forming a conductive layer to fill the opening and cover an upper surface of the mask; and patterning the conductive layer and removing the mask to form the first electrode. However, Kim et al (figs. 13A-15A) disclose forming the first electrode (265, pp [0057]) comprises: forming a conductive layer to fill the opening and cover an upper surface of the mask (262, pp [0056]); and patterning the conductive layer and removing the mask to form the first electrode (265A, pp [0058]). Therefore, it would have been obvious to one skill in the art to combine the teaching as taught by Kim et al into the method of Cho et al to provide the known purpose of reducing the method step. With respect to claim 9, Kim et al (figs. 13A-15A) disclose wherein the portion of the conductive layer (265A, pp [0058]) and the mask (262, pp [0056]) are removed by a chemical mechanical polishing technique (pp [0058]). With respect to claim 10, Kim et al (figs. 13A-15A) disclose wherein the upper surface of the first electrode (265A, pp [0058]) is substantially aligned with an upper surface of the upper sacrifice layer (260, pp [0058]) after removing the portion of the conductive layer and the mask. Allowable Subject Matter Claims 3-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: the prior art of record fails to wherein forming the upper supporting layer comprises: forming a dielectric layer to cover the upper surface and the lateral surface of the first electrode; and removing a first portion of the dielectric layer, which is over the first electrode, to form the upper supporting layer. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HOAI V PHAM whose telephone number is (571)272-1715. The examiner can normally be reached M-F 8:30a.m-10:00p.m. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Drew Richards can be reached at 571-271-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HOAI V PHAM/Primary Examiner, Art Unit 2892
Read full office action

Prosecution Timeline

Jul 12, 2024
Application Filed
Sep 10, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12740468
BONDING WIRE FOR SEMICONDUCTOR DEVICES
2y 9m to grant Granted Sep 15, 2026
Patent 12733152
SEMICONDUCTOR DEVICES AND FABRICATING METHODS THEREOF
3y 1m to grant Granted Sep 08, 2026
Patent 12733157
SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME
3y 0m to grant Granted Sep 08, 2026
Patent 12733230
METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
2y 9m to grant Granted Sep 08, 2026
Patent 12733530
BONDING WIRE FOR SEMICONDUCTOR DEVICES
2y 8m to grant Granted Sep 08, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
89%
Grant Probability
88%
With Interview (-1.2%)
2y 0m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 712 resolved cases by this examiner. Grant probability derived from career allowance rate.

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