DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 9-13 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 10-16 of U.S. Patent No. 10,497,628. Although the claims at issue are not identical, they are not patentably distinct from each other because all the limitations recited within claims 9-13 of the present invention are recited within claims 10-16 of U.S. Patent No. 10,497,628.
Application: 18/770,919 (present Application)
U.S. Patent No. 10,497,628
(reference)
Claim 9: A method, comprising: providing a first fin structure on a semiconductor substrate in a first region for forming p- type metal-oxide-semiconductor (PMOS) devices and a second fin structure on the semiconductor substrate in a second region for forming n-type metal-oxide-semiconductor (NMOS) devices, wherein the second region spans a greater area than the first region, wherein lower portions of the first fin structure and the second fin structure are surrounded by an isolation feature;
Claims 10 and 11 teach: a method, comprising: providing a first fin structure on a semiconductor substrate in a first region for forming p-type metal-oxide-semiconductor (PMOS) devices and a second fin structure on the semiconductor substrate in a second region for forming n-type metal-oxide-semiconductor (NMOS) devices, wherein the first fin structure and the second fin structure are separated by isolation features; and wherein the first fin structure comprises one fin and the second fin structure comprises two fins connected at bottom of the two fins (since this limitation includes “the second fin structure comprises two fins connected at bottom of the two fins” which provides the same meaning of “wherein the second region spans a greater area than the first region” as recited in claim 9 of the present invention) (see claims 10 and 11);
forming a first patterned etch mask layer over the second region thereby exposing the first region;
“forming a first patterned etch mask layer over the second region thereby exposing the first region” (see claim 10)
removing a portion of the first fin structure to form a recessed first fin structure;
“removing a portion of the first fin structure to form a recessed first fin structure” (see claim 10);
forming a first source/drain feature on a top surface of the recessed first fin structure;
“forming a first source/drain feature on a top surface of the recessed first fin structure” (see claim 10);
subsequent to forming the first source/drain feature, forming a second patterned etch
mask layer over the first region thereby exposing the second region;
“subsequent to removing the first hard mask layer, forming a second hard mask layer over the first source/drain feature, the second fin structure, and the isolation features; subsequent to forming the second hard mask layer, forming a second patterned etch mask over the first region thereby exposing the second region” (see claim 10).
removing a portion of the second fin structure to form a recessed second fin structure;
“removing a portion of the second fin structure to form a recessed second fin structure; forming a second source/drain feature on a top surface of the recessed second fin structure” (see claim 10); and
and forming a second source/drain feature on a top surface of the recessed second fin structure.
“forming a second source/drain feature on a top surface of the recessed second fin structure” (see claim 10).
Claim 10: The method of claim 9, further comprising: before forming the first patterned etch mask layer, forming a first hard mask layer over the first fin structure, the second fin structure, and the isolation feature;
“forming a first hard mask layer over the first fin structure, the second fin structure, and the isolation features; forming a first patterned etch mask layer over the second region thereby exposing the first region” (see claim 10);
and after the forming of the first source/drain feature, removing the first hard mask layer.
“forming a first source/drain feature on a top surface of the recessed first fin structure; removing the first hard mask layer from the second fin structure and the isolation features surrounding the second fin structure” (see claim 10).
Claim 11: The method of claim 10, further comprising: before forming the second patterned etch mask layer, forming a second hard mask layer over the first source/drain feature, the second fin structure, and the isolation feature;
“forming a second hard mask layer over the first source/drain feature, the second fin structure, and the isolation features; subsequent to forming the second hard mask layer, forming a second patterned etch mask over the first region thereby exposing the second region” (see claim 10).
12. The method of claim 10, wherein the first source/drain feature is formed to have a single epitaxial feature, and the second source/drain feature is formed to have multiple epitaxial features merged together.
Claim 11 of the reference recites: “wherein the first fin structure comprises one fin and the second fin structure comprises two fins connected at bottom of the two fins”, thus it’s inherent to include “the first source/drain feature is formed to have a single epitaxial feature, and the second source/drain feature is formed to have multiple epitaxial features merged together” as recited in claim 12 of the present invention.
13. The method of claim 10, wherein the removing of the portions of the first and the second fin structures also etches the isolation feature, and
“wherein removing the portion of the first fin structure comprises removing isolation features in the first region to form a first recessed region, wherein removing the portion of the second fin structure comprises removing isolation features in the second region to form a second recessed region” (see claim 14)
the etching of the isolation feature causes the isolation feature between the first source/drain feature and the second source/drain feature to have a hump shape.
“wherein a lowest point of the first recessed region and the second recessed region is closer to the first source/drain feature than to the second source/drain feature” (recited in claim 14 of the reference) which creates “the isolation feature between the first source/drain feature and the second source/drain feature to have a hump shape” after the etching of the isolation feature as recited in claim 13 of the present invention (see claim 14 - reference).
Allowable Subject Matter
Claims 14-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 1-8, and 17-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
A method, comprising: lower portions of the first fin structure and the second fin structure are surrounded by an isolation feature; recessing the first fin structure to a first height, wherein recessing the first fin structure forms a first recessed region in the isolation feature; epitaxially growing a p-type source/drain feature on the recessed first fin structure; subsequent to epitaxially growing the p-type source/drain feature, recessing the second fin structure to a second height, wherein the second height is above the first height, wherein recessing the second fin structure forms a second recessed region in the isolation feature; and epitaxially growing an n-type source/drain feature on the recessed second fin structure, in combination with other claimed features, as recited in independent claim 1. Claims 2-8 are dependent upon independent claim 1, and are therefore allowed.
A method comprising: lower portions of the first fin structure and the second fin structure are surrounded by an isolation feature; recessing the first fin structure, wherein recessing the first fin structure forms a first recessed region in the isolation feature; forming a first source/drain feature on the recessed first fin structure, wherein the first source/drain feature includes a p-type epitaxial semiconductor structure; subsequent to forming the first source/drain feature, recessing the second fin structure, wherein recessing the second fin structure forms a second recessed region in the isolation feature, and wherein after the recessing of the second fin structure, the isolation feature includes a first portion closer to the first fin structure, a second portion closer to the second fin structure, and a middle portion between the first and second portions, and the first and second portions have top surfaces that extends upwards to a top surface of the middle portion; and forming a second source/drain feature on the recessed second fin structure, wherein the second source/drain feature includes an n-type epitaxial semiconductor structure, in combination with other claimed features, as recited in independent claim 17. Claims 18-20 are dependent upon independent claim 17, and are therefore allowed.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANH Y TRAN whose telephone number is (571)272-2110. The examiner can normally be reached on M-F, 10am-10pm (flex) (PST).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached on (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Thanh Y. Tran/Primary Examiner, Art Unit 2817 July 25, 2026