DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/12/2024, 11/22/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
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Claims 1, 4-12, 14-17 and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 5-6, 8 and 11-12 of U.S. Patent No. 12,131,954. Although the claims at issue are not identical, they are not patentably distinct from each other because the conflicting claims have been patented.
Regarding claim 1, Pat '954 discloses, in claim 1, a method comprising:
forming Complementary Field-Effect Transistors comprising: a lower transistor comprising a lower source/drain region; and an upper transistor comprising an upper source/drain region (all limitations are the same with the limitations recited in claim 1 of Pat '954);
etching a dielectric layer over a lower dielectric layer between the upper source/drain region and the lower source/drain region to form an opening, wherein a top surface of the lower source/drain region is exposed to the opening ("etching an upper dielectric layer over the upper source/drain region and a lower dielectric layer between the upper source/drain region and the lower source/drain region to form an opening, wherein a sidewall of the upper source/drain region and a top surface of the lower source/drain region are exposed to the opening", in claim 1 of Pat '954, is interpreted as the same limitation);
performing an epitaxy process to form a first semiconductor layer on the lower source/drain region, wherein the first semiconductor layer and the lower source/drain region collectively form a combined source/drain region ("performing an epitaxy process to form: a first semiconductor layer on the sidewall of the upper source/drain region; and a second semiconductor layer on the top surface of the lower source/drain region; removing the first semiconductor layer, with the second semiconductor layer being remaining, wherein the second semiconductor layer and the lower source/drain region collectively form a combined source/drain region", in claim 1 of Pat '954, is interpreted as the same limitation); and
forming a contact plug in the opening to electrically connect to the combined source/drain region ("forming a contact plug in the opening, wherein the contact plug electrically connects the upper source/drain region to the combined source/drain region", in claim 1 of Pat '954, is interpreted as the same limitation).
Regarding claim 4, Pat '954 discloses the method of claim 1 as described above.
Pat '954 further discloses, in claim 2, the upper source/drain region is of a first conductivity type, the lower source/drain region is of a second conductivity type opposite to the first conductivity type, and wherein in the epitaxy process, the first semiconductor layer is in-situ doped with a dopant of the second conductivity type ("the upper source/drain region is of a first conductivity type, the lower source/drain region is of a second conductivity type opposite to the first conductivity type, and wherein in the epitaxy process, the first semiconductor layer and the second semiconductor layer are in-situ doped with a dopant of the second conductivity type", in claim 2 of Pat '954, is interpreted as the same limitation).
Regarding claim 5, Pat '954 discloses the method of claim 1 as described above.
Pat '954 further discloses, in claim 1, in the epitaxy process, a second semiconductor layer is deposited on a sidewall of the upper source/drain region ("performing an epitaxy process to form: a first semiconductor layer on the sidewall of the upper source/drain region; and a second semiconductor layer on the top surface of the lower source/drain region; removing the first semiconductor layer, with the second semiconductor layer being remaining, wherein the second semiconductor layer and the lower source/drain region collectively form a combined source/drain region", in claim 1 of Pat '954, is interpreted as the same limitation).
Regarding claim 6, Pat '954 discloses the method of claim 5 as described above.
Pat '954 further discloses, in claim 8, in the epitaxy process, a vertical growth rate of the second semiconductor layer in a vertical direction is higher than a horizontal growth rate of the second semiconductor layer ("the epitaxy process is performed with a vertical growth rate being greater than a horizontal growth rate", in claim 8 of Pat '954, is interpreted as the same limitation).
Regarding claim 7, Pat '954 discloses the method of claim 5 as described above.
Pat '954 further discloses, in claims 1 and 3, forming a sacrificial region over the first semiconductor layer; and performing an etching process to remove the second semiconductor layer, wherein in the etching process, the sacrificial region protects the first semiconductor layer from being etched ("performing an epitaxy process to form: a first semiconductor layer on the sidewall of the upper source/drain region; and a second semiconductor layer on the top surface of the lower source/drain region; removing the first semiconductor layer, with the second semiconductor layer being remaining, wherein the second semiconductor layer and the lower source/drain region collectively form a combined source/drain region" and “the first semiconductor layer is removed by processes comprising: forming a sacrificial layer to fill the opening; recessing the sacrificial layer, so that the first semiconductor layer is revealed, and the second semiconductor layer is covered by the sacrificial layer; etching the first semiconductor layer; and removing the sacrificial layer”, in claims 1 and 3 of Pat '954, are interpreted as the same limitation).
Regarding claim 8, Pat '954 discloses the method of claim 7 as described above.
Pat '954 further discloses, in claim 3, after the second semiconductor layer is removed, removing the sacrificial region ("the first semiconductor layer is removed by processes comprising: forming a sacrificial layer to fill the opening; recessing the sacrificial layer, so that the first semiconductor layer is revealed, and the second semiconductor layer is covered by the sacrificial layer; etching the first semiconductor layer; and removing the sacrificial layer", in claim 8 of Pat '954, is interpreted as the same limitation).
Regarding claim 9, Pat '954 discloses the method of claim 1 as described above.
Pat '954 further discloses, in claim 5, the lower source/drain region is grown at a first wafer temperature, wherein the epitaxy process is performed at a second wafer temperature lower than the first wafer temperature ("epitaxially growing the lower source/drain region and the upper source/drain region at a first wafer temperature, wherein the epitaxy process is performed at a second wafer temperature lower than the first wafer temperature", in claim 5 of Pat '954, is interpreted as the same limitation).
Regarding claim 10, Pat '954 discloses, in claims 1 and 11, a method comprising:
forming a first transistor comprising a first source/drain region; forming a second transistor comprising a second source/drain region adjacent to the first transistor; after both of the first source/drain region and the second source/drain region are formed, performing an epitaxy process to grow a first semiconductor layer on the first source/drain region ("forming Complementary Field-Effect Transistors comprising: a lower transistor comprising a lower source/drain region; and an upper transistor comprising an upper source/drain region; performing an epitaxy process to form: a first semiconductor layer on the sidewall of the upper source/drain region; and a second semiconductor layer on the top surface of the lower source/drain region; removing the first semiconductor layer, with the second semiconductor layer being remaining, wherein the second semiconductor layer and the lower source/drain region collectively form a combined source/drain region", in claim 1 of Pat '954, is interpreted as the same limitation);
siliciding the first semiconductor layer to form a first silicide layer; siliciding the second source/drain region to form a second silicide layer; and forming a contact plug to electrically connect to the first silicide layer ("forming a contact plug in the opening, wherein the contact plug electrically connects the upper source/drain region to the combined source/drain region" and “before the contact plug is formed: forming a lower silicide layer on the second semiconductor layer; and forming an upper silicide layer on the sidewall of the upper source/drain region”, in claims 1 and 11 of Pat '954, are interpreted as the same limitation).
Regarding claim 11, Pat '954 discloses the method of claim 10 as described above.
Pat '954 further discloses, in claims 1 and 11, during the epitaxy process, a second semiconductor layer is grown on the second source/drain region, and wherein the method further comprises, before the first silicide layer and the second silicide layer are formed, removing the second semiconductor layer ("performing an epitaxy process to form: a first semiconductor layer on the sidewall of the upper source/drain region; and a second semiconductor layer on the top surface of the lower source/drain region; removing the first semiconductor layer, with the second semiconductor layer being remaining, wherein the second semiconductor layer and the lower source/drain region collectively form a combined source/drain region" and “before the contact plug is formed: forming a lower silicide layer on the second semiconductor layer; and forming an upper silicide layer on the sidewall of the upper source/drain region”, in claims 1 and 11 of Pat '954, are interpreted as the same limitation).
Regarding claim 12, Pat '954 discloses the method of claim 10 as described above.
Pat '954 does not explicitly disclose the second transistor overlaps the first transistor.
Pat '954 teaches, in claim 12, the second transistor overlaps the first transistor ("an upper source/drain region overlapping the lower source/drain region", in claim 12 of Pat '954, is interpreted as the same limitation), for the purpose of reducing the difficult in the formation of the local interconnect with the reduction of the aspect ratio.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in claim 1 of Pat '954 to have the second transistor overlapping the first transistor, as taught by claim 12 of Pat '954, for the purpose of reducing the difficult in the formation of the local interconnect with the reduction of the aspect ratio.
Regarding claim 14, Pat '954 discloses the method of claim 10 as described above.
Pat '954 further discloses, in claim 1, the contact plug electrically connects the first source/drain region to the second transistor ("the contact plug electrically connects the upper source/drain region to the combined source/drain region", in claim 1 of Pat '954, is interpreted as the same limitation).
Regarding claim 15, Pat '954 discloses the method of claim 10 as described above.
Pat '954 further discloses, in claim 5, the first source/drain region is grown at a first wafer temperature, and the first semiconductor layer is grown at a second wafer temperature lower than the first wafer temperature ("epitaxially growing the lower source/drain region and the upper source/drain region at a first wafer temperature, wherein the epitaxy process is performed at a second wafer temperature lower than the first wafer temperature", in claim 5 of Pat '954, is interpreted as the same limitation).
Regarding claim 16, Pat '954 discloses the method of claim 15 as described above.
Pat '954 further discloses, in claim 6, the epitaxy process is performed at the second wafer temperature in a range between about 200oC and about 400oC ("the epitaxy process is performed at a wafer temperature in a range between about 200oC and about 400oC", in claim 6 of Pat '954, is interpreted as the same limitation).
Regarding claim 17, Pat '954 discloses, in claim 1, a method comprising:
forming Complementary Field-Effect Transistors comprising: forming a lower transistor comprising a lower source/drain region; and forming an upper transistor comprising an upper source/drain region; after both of the lower transistor and the upper transistor are formed, forming a semiconductor layer over and contacting the lower source/drain region ("forming Complementary Field-Effect Transistors comprising: a lower transistor comprising a lower source/drain region; and an upper transistor comprising an upper source/drain region; performing an epitaxy process to form: a first semiconductor layer on the sidewall of the upper source/drain region; and a second semiconductor layer on the top surface of the lower source/drain region; removing the first semiconductor layer, with the second semiconductor layer being remaining, wherein the second semiconductor layer and the lower source/drain region collectively form a combined source/drain region", in claim 1 of Pat '954, is interpreted as the same limitation);
Pat '954 does not explicitly disclose siliciding a top part of the semiconductor layer to form a silicide layer; forming a contact plug over the silicide layer.
Pat '954 teaches, in claim 12, siliciding a top part of the semiconductor layer to form a silicide layer; forming a contact plug over the silicide layer ("a lower silicide layer on the first top surface of the upper portion of the lower source/drain region; a contact plug contacting both of the upper silicide layer and the lower silicide layer", in claim 12 of Pat '954, is interpreted as the same limitation), for the purpose of reducing the difficult in the formation of the local interconnect with the reduction of the aspect ratio.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in claim 1 of Pat '954 to have the siliciding a top part of the semiconductor layer to form a silicide layer; the forming a contact plug over the silicide layer, as taught by claim 12 of Pat '954, for the purpose of reducing the difficult in the formation of the local interconnect with the reduction of the aspect ratio.
Regarding claim 20, Pat '954 discloses the method of claim 17 as described above.
Pat '954 further discloses, in claim 1, the semiconductor layer is formed through epitaxy ("performing an epitaxy process to form: a first semiconductor layer on the sidewall of the upper source/drain region; and a second semiconductor layer on the top surface of the lower source/drain region; removing the first semiconductor layer, with the second semiconductor layer being remaining, wherein the second semiconductor layer and the lower source/drain region collectively form a combined source/drain region", in claim 1 of Pat '954, is interpreted as the same limitation).
Allowable Subject Matter
Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1 and 2 that recite "an entirety of the first semiconductor layer is grown in the opening" in combination with other elements of the base claims 1 and 2.
Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1 and 3 that recite "the first semiconductor layer is grown until a top surface of the first semiconductor layer is at a level between a bottom surface and a top surface of the dielectric layer" in combination with other elements of the base claims 1 and 3.
Claim 13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 10 and 13 that recite "etching the CESL and the ILD to form a contact opening, wherein the first semiconductor layer is grown in the contact opening" in combination with other elements of the base claims 10 and 13.
Claim 18 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 17 and 18 that recite "at a time after the semiconductor layer is formed, the upper source/drain region is free from the semiconductor layer thereon" in combination with other elements of the base claims 17 and 18.
Claim 19 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 17 and 19 that recite "the semiconductor layer has opposing edges laterally recessed from respective edges of the lower source/drain region" in combination with other elements of the base claims 17 and 19.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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/TONG-HO KIM/Primary Examiner, Art Unit 2811
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