Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “Semiconductor Chip Package Including Stacked Redistribution Layers and Local Interconnects”.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1-3, 5 and 18-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. US 12,080,563 B2, hereinafter Chen563.
Although the claims at issue are not identical, they are not patentably distinct from each other because the parent patent renders obvious the instant application.
Regarding independent claim 1: Chen563 teaches (e.g., Claims 1-20) a method comprising:
forming a first metallization layer; forming a first conductive through via on the first metallization layer;
mounting a local interconnect device on the first metallization layer, the local interconnect device including a substrate and a through substrate via extending partially through the substrate;
encapsulating the local interconnect device and the first conductive through via in a first encapsulant;
performing a planarization process wherein a portion of the first encapsulant is removed to expose a top surface of the first conductive through via and wherein a portion of the first encapsulant and a portion of the substrate is removed to expose the through substrate via, and wherein a top surface of the first conductive through via and a top surface of the through substrate via are coplanar as a result of the planarization process;
forming a second conductive through via over the first encapsulant, the second conductive through via being aligned to and electrically connected to the first conductive via; forming a third conductive through via over the first encapsulant, the third conductive through via being aligned to and electrically connected to the through substrate via,
the third conductive through via having a width that is less than a width of the second conductive through via; and encapsulating the second conductive through via and the third conductive through via in a second encapsulant (Claim 2).
Regarding claim 2: Chen563 teaches the claim limitation of the method of claim 1, on which this claim depends,
wherein the step of forming the first metallization layer includes: forming at least one patterned dielectric layer over a substrate; depositing a patterned metallization layer on each patterned dielectric layer; and wherein the first metallization layer is a topmost one of the patterned metallization layers (Claim 2).
Regarding claim 3: Chen563 teaches the claim limitation of the method of claim 1, on which this claim depends,
wherein the step of forming the first conductive through via includes: forming a seed layer on the first metallization layer; forming a patterned masking layer over the seed layer, the patterned masking layer leaving a portion of the seed layer exposed; plating the first conductive through via onto the exposed portion of the seed layer; and removing the patterned masking layer.
Regarding claim 5: Chen563 teaches the claim limitation of the method of claim 1, on which this claim depends,
wherein the step of encapsulating the local interconnect device and the first conductive through via in the first encapsulant includes: placing the local interconnect device and the first conductive through via in a mold; injecting a liquid molding compound into the mold; and curing the liquid molding compound (Claim 2).
Regarding independent claim 18: Chen563 teaches (e.g., Claims 8-14) a device comprising:
a first redistribution layer including: at least one first metallization layer embedded at least partially within a first dielectric layer;
a local interconnect layer on a first side of the first redistribution layer, the local interconnect layer including:
a local interconnect substrate, a through substrate via extending through the local interconnect substrate, a conductive connector bonded to the first metallization layer;
a first conductive through via adjacent the local interconnect substrate and bonded to the first metallization layer, and
a first encapsulant surrounding the local interconnect substrate and the first conductive through via,
wherein the first encapsulant, the through substrate via, and the first conductive through via have co-planar top surfaces; a local interconnect structure in the local interconnect layer, the local interconnect structure including: a second dielectric layer on the first encapsulant,
the local interconnect substrate, and the first conductive through via, the second dielectric layer being patterned to expose the through substrate via and the first conductive through via, and a second metallization layer electrically contacting the through substrate via and the first conductive through via; and a second redistribution structure on the local interconnect layer, the second redistribution structure including: a second conductive through via aligned with and electrically connected to the first conductive through via by way of the second metallization layer,
a third conductive through via aligned with and electrically connected to the through substrate via by way of the second metallization layer,
wherein the second conductive via has a width that is less the first conductive through via, and a second encapsulant on the second dielectric layer and surrounding the third conductive through via and the third conductive through via (Claim 8).
Regarding claim 19: Chen563 teaches the claim limitation of the device of claim 18, on which this claim depends,
further comprising an interposer mounted on the second redistribution structure (Claim 9).
Regarding claim 20: Chen563 teaches the claim limitation of the device of claim 19, on which this claim depends,
further comprising an integrated circuit device mounted to a second side, opposite the first side, of the first redistribution layer, wherein a first contact pad of the integrated circuit device is electrically connected to a second contact pad of the integrated circuit device through the local interconnect structure (Claim 10).
Claims 1, 4 and 6-17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of US 11,515,173 B2 to Chen et al., hereinafter Chen173.
Regarding independent claim 1: Chen173 teaches (e.g., Claims 1-7) a method comprising:
forming a first metallization layer; forming a first conductive through via on the first metallization layer;
mounting a local interconnect device on the first metallization layer, the local interconnect device including a substrate and a through substrate via extending partially through the substrate;
encapsulating the local interconnect device and the first conductive through via in a first encapsulant;
performing a planarization process wherein a portion of the first encapsulant is removed to expose a top surface of the first conductive through via and wherein a portion of the first encapsulant and a portion of the substrate is removed to expose the through substrate via, and
wherein a top surface of the first conductive through via and a top surface of the through substrate via are coplanar as a result of the planarization process;
forming a second conductive through via over the first encapsulant, the second conductive through via being aligned to and electrically connected to the first conductive via; forming a third conductive through via over the first encapsulant, the third conductive through via being aligned to and electrically connected to the through substrate via,
the third conductive through via having a width that is less than a width of the second conductive through via; and encapsulating the second conductive through via and the third conductive through via in a second encapsulant (Claim 1).
Regarding claim 4: Chen173 teaches the claim limitation of the method of claim 1, on which this claim depends,
wherein the local interconnect device has contact pads thereon, the method further comprising: aligning the contact pads on the local interconnect device to corresponding contact pads formed in the first metallization layer; and bonding the contact pads on the local interconnect device to the corresponding contact pads in the first metallization layer (Claim 6).
Regarding independent claim 1: Chen173 teaches (e.g., Claims 16-20) a method comprising:
forming a first metallization layer; forming a first conductive through via on the first metallization layer;
mounting a local interconnect device on the first metallization layer, the local interconnect device including a substrate and a through substrate via extending partially through the substrate;
encapsulating the local interconnect device and the first conductive through via in a first encapsulant;
performing a planarization process wherein a portion of the first encapsulant is removed to expose a top surface of the first conductive through via and wherein a portion of the first encapsulant and a portion of the substrate is removed to expose the through substrate via, and
wherein a top surface of the first conductive through via and a top surface of the through substrate via are coplanar as a result of the planarization process;
forming a second conductive through via over the first encapsulant, the second conductive through via being aligned to and electrically connected to the first conductive via; forming a third conductive through via over the first encapsulant, the third conductive through via being aligned to and electrically connected to the through substrate via,
the third conductive through via having a width that is less than a width of the second conductive through via; and encapsulating the second conductive through via and the third conductive through via in a second encapsulant (Claim 16).
Regarding claim 6: Chen173 teaches the claim limitation of the method of claim 1, on which this claim depends,
wherein the step of forming the second conductive through via further includes: forming a dielectric layer over the first encapsulant; depositing a second metallization layer over the dielectric layer, the second metallization layer being in contact with the first conductive through via; depositing a seed layer on the second metallization layer; and plating the second conductive via onto the seed layer (Claim 17).
Regarding claim 7: Chen173 teaches the claim limitation of the method of claim 6, on which this claim depends,
wherein the step of encapsulating the second conductive through via and the third conductive through via in the second encapsulant further includes: placing a laminate sheet of encapsulant material over exposed surfaces of the second conductive through via, the third conductive through via, and the second metallization layer; and laminating the laminate sheet of encapsulant material to the exposed surfaces of the second conductive through via, the third conductive through via, and the second metallization layer (Claim 9).
Regarding independent claim 1: Chen173 teaches (e.g., Claims 8-15) a method comprising:
forming a first metallization layer; forming a first conductive through via on the first metallization layer;
mounting a local interconnect device on the first metallization layer, the local interconnect device including a substrate and a through substrate via extending partially through the substrate;
encapsulating the local interconnect device and the first conductive through via in a first encapsulant;
performing a planarization process wherein a portion of the first encapsulant is removed to expose a top surface of the first conductive through via and wherein a portion of the first encapsulant and a portion of the substrate is removed to expose the through substrate via, and
wherein a top surface of the first conductive through via and a top surface of the through substrate via are coplanar as a result of the planarization process;
forming a second conductive through via over the first encapsulant, the second conductive through via being aligned to and electrically connected to the first conductive via; forming a third conductive through via over the first encapsulant, the third conductive through via being aligned to and electrically connected to the through substrate via,
the third conductive through via having a width that is less than a width of the second conductive through via; and
encapsulating the second conductive through via and the third conductive through via in a second encapsulant (Claim 8).
Regarding claim 8: Chen173 teaches the claim limitation of the method of claim 1, on which this claim depends, further comprising:
forming a redistribution structure over the second encapsulant and in contact with the second conductive through via and the third conductive through via, the redistribution structure including a stack of redistribution metallization layers embedded within respective redistribution dielectric layers;
depositing a passivation layer over the redistribution structure, the passivation layer exposing portions of a top redistribution metallization layer of the stack of redistribution metallization layers; and
forming a solder connector over the passivation layer and in electrical contact with the exposed portions of the top redistribution metallization layer (Claim 11).
Regarding independent claim 9: Chen173 teaches (e.g., Claims 16-20) a method comprising: forming a first redistribution structure, the first redistribution structure including at least one first metallization layer embedded within a first redistribution dielectric;
mounting on a first side of the first redistribution structure a first conductive through via and a local interconnect structure, the local interconnect structure including a substrate and a conductive through substrate via extending partially through the substrate;
encapsulating the first conductive through via, the local interconnect structure, and at least a top portion of the first redistribution structure in a first encapsulant;
planarizing the first encapsulant, the first conductive through via, and the local interconnect structure,
wherein the planarizing exposes the conductive through via at a backside of the substrate;
mounting a second conductive through via on the first conductive through via and a third conductive through via on the through substrate via; encapsulating the second conductive through via and the third conductive through via in a second encapsulant; forming a second redistribution structure on the second encapsulant, the second redistribution structure including at least one second metallization layer embedded within a second redistribution dielectric;
bonding an interposer to the second redistribution structure,
the interposer including a core substrate, a first routing structure on a first side of the core substrate and a second routing structure on a second opposite side of the core substrate; and bonding to a second side of the first redistribution structure, opposite the first side, an integrated circuit device,
wherein a first contact pad of the integrated circuit device is electrically connected to a second contact pad of the integrated circuit device through the local interconnect structure, and wherein a third contact pad of the integrated circuit device is electrically connected to an external connector through the first conductive through via (Claim 16).
Regarding claim 10: Chen173 teaches the claim limitation of the method of claim 9, on which this claim depends, further comprising:
wherein the step of mounting on the first side of the first redistribution structure the first conductive through via includes forming a seed layer on the first side of the first redistribution structure and plating the first conductive via onto the seed layer (Claim 17).
Regarding claim 11: Chen173 teaches the claim limitation of the method of claim 9, on which this claim depends, further comprising:
wherein the third conductive via and the second conductive via are formed simultaneously, and further wherein the third conductive through via has a width that is less than a width of the second conductive through via (Claim 16).
Regarding independent claim 9: Chen173 teaches (e.g., Claims 8-15) a method comprising: forming a first redistribution structure, the first redistribution structure including at least one first metallization layer embedded within a first redistribution dielectric;
mounting on a first side of the first redistribution structure a first conductive through via and a local interconnect structure, the local interconnect structure including a substrate and a conductive through substrate via extending partially through the substrate;
encapsulating the first conductive through via, the local interconnect structure, and at least a top portion of the first redistribution structure in a first encapsulant;
planarizing the first encapsulant, the first conductive through via, and the local interconnect structure,
wherein the planarizing exposes the conductive through via at a backside of the substrate;
mounting a second conductive through via on the first conductive through via and a third conductive through via on the through substrate via; encapsulating the second conductive through via and the third conductive through via in a second encapsulant; forming a second redistribution structure on the second encapsulant, the second redistribution structure including at least one second metallization layer embedded within a second redistribution dielectric;
bonding an interposer to the second redistribution structure,
the interposer including a core substrate, a first routing structure on a first side of the core substrate and a second routing structure on a second opposite side of the core substrate; and bonding to a second side of the first redistribution structure, opposite the first side, an integrated circuit device, wherein a first contact pad of the integrated circuit device is electrically connected to a second contact pad of the integrated circuit device through the local interconnect structure, and wherein a third contact pad of the integrated circuit device is electrically connected to an external connector through the first conductive through via (Claim 8)
Regarding claim 12: Chen173 teaches the claim limitation of the method of claim 9, on which this claim depends, further comprising:
wherein the step of mounting the second conductive through via on the first conductive through via and the third conductive through via on the through substrate via includes: depositing a passivation layer on the first encapsulant; forming a patterned metallization layer on the passivation layer, the patterned metallization layer including a first feature extending through the passivation layer and contacting the first conductive through via, the patterned metallization layer further including a second feature extending through the passivation layer and contacting the conductive through substrate via; and plating the second conductive through via on the first feature and plating the third conductive through via on the second feature (Claim 12).
Regarding claim 13: Chen173 teaches the claim limitation of the method of claim 9, on which this claim depends,
wherein the step of encapsulating the second conductive through via and the third conductive through via in the second encapsulant includes placing a laminate sheet of encapsulant material over exposed surfaces of the second conductive through via and the third conductive through via; and laminating the laminate sheet of encapsulant material to the exposed surfaces of the second conductive through via and the third conductive through via (Claim 11).
Regarding claim 14: Chen173 teaches the claim limitation of the method of claim 9, on which this claim depends,
wherein the step of mounting on the first side of the first redistribution structure the first conductive through via and the local interconnect structure includes solder bonding the local interconnect structure to the first redistribution structure (Claim 15).
Regarding claim 15: Chen173 teaches the claim limitation of the method of claim 9, on which this claim depends,
wherein the step of bonding to the second side of the first redistribution structure, opposite the first side, the integrated circuit device includes thermos-compression bonding the integrated circuit device to the first redistribution structure (Claim 15).
Regarding claim 16: Chen173 teaches the claim limitation of the method of claim 9, on which this claim depends,
further including filling a gap between the integrated circuit device and the first redistribution structure with an underfill material (Claim 9).
Regarding claim 17: Chen173 teaches the claim limitation of the method of claim 9, on which this claim depends,
further comprising mounting on the first side of the first redistribution structure a second local interconnect structure, and further wherein a fourth contact pad of the integrated circuit device is electrically connected to a fifth contact pad of the integrated circuit device through the second local interconnect structure (Claim 15).
Allowable Subject Matter
Claims 1-20 are rejected under nonstatutory double patenting but, would be allowable if all rejected claims are overcome.
Conclusion
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/HERVE-LOUIS Y ASSOUMAN/Examiner, Art Unit 2812
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