DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. 17/353,380, filed on 06/21/2021.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, 4, 8, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Chung et al. (US 20180130905 A1; hereinafter Chung) in view of Tsai et al. (US 20170110324 A1; hereinafter Tsai).
Regarding claim 1, FIGS. 4-6 of Chung teach a semiconductor device (e.g. FIG. 6) comprising: a gate electrode (130/1140 ¶ [0044]) over a semiconductor fin (110 ¶ [0107]); a first capping layer (147) over the gate electrode (130/1140 ¶ [0107]); and a second capping layer (1130) over the first capping layer (147 ¶ [0044]), the second capping layer (1130) comprising: a first liner (1135a ¶ [0099]); a second capping layer material (1131b ¶ [0080]); and a second liner (1135b) over the second capping layer material (1131b ¶ [0099]), the second liner (1135b) being coplanar with a dielectric layer (280 ¶ [0148]), wherein the first liner (1135a) and the second liner (1135b) are crystalline (¶ [0099]).
Chung does not explicitly teach the second capping layer material being free from voids.
FIG. 2 of Tsai teaches a method of forming a second capping layer (¶ [0028] “conformal metal gate layers”) using ALD processing (¶ [0028]), the second capping layer (“conformal metal gate layers”) being free from voids (¶ [0028]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught by Chung with the void-free metal layer taught by Tsai for the purpose of preventing degradation of device performance (¶ [0028]).
Regarding claim 2, Chung as modified teaches the semiconductor device of claim 1, and FIG. 6 of Chung further teaches wherein the first capping layer (147) comprises: a first liner (145); and a first gate mask material (146 ¶ [0133]).
Regarding claim 4, Chung as modified teaches the semiconductor device of claim 3, and FIG. 6 of Chung further teaches wherein the first gate mask material (146) comprises silicon oxide (¶ [0135]).
Regarding claim 8, FIGS. 4-6 of Chung teach a semiconductor device (e.g. FIG. 6) comprising: a first gate electrode (130/1140 ¶ [0044]) over a semiconductor fin (110 ¶ [0107]); a first capping layer (147) over the first gate electrode (130/1140 ¶ [0107]) within a first opening of a dielectric layer (opening of 180 ¶ [0144]); a first liner (1135a ¶ [0099]) within the first opening (opening of 180) over the first capping layer (147), wherein the first liner (1135a) is crystalline (¶ [0099]); a gate mask material (1131b ¶ [0099]) within the first opening (opening of 180); and a second liner (1135b ¶ [0099]) within the first opening (opening of 180) over and in physical contact with both the gate mask material (1131b) and the first liner (1135a), wherein the second liner (1135b) is crystalline (¶ [0099]). The Examiner notes the limitation “in physical contact” has been interpreted under broadest reasonable interpretation (BRI, MPEP § 2111.01) as “in direct physical contact” or “in indirect physical contact”.
Chung as modified does not explicitly teach a void-free gate mask material.
FIG. 2 of Tsai teaches a method of forming a void-free gate mask material (¶ [0028] “conformal metal gate layers”) using ALD processing (¶ [0028]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught by Chung with the void-free metal layer taught by Tsai for the purpose of preventing degradation of device performance (¶ [0028]).
Regarding claim 10, Chung as modified teaches the semiconductor device of claim 8, and Chung further teaches wherein the first liner (1135a) is a first material (e.g. TiSiN) and the second liner (1135b) is the first material (e.g. TiSiN ¶ [0099]).
Claims 3, 7, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Chung in view of Tsai, and further in view of Bae et al. (US 20220077292 A1; hereinafter Bae).
Regarding claim 3, Chung as modified teaches the semiconductor device of claim 2.
Chung as modified does not teach wherein the first liner comprises silicon carbonitride.
FIG. 2 of Bae teaches a transistor device comprising: a gate electrode (110 ¶ [0034]) and a first liner (113) over the gate electrode (110 ¶ [0034]), wherein the first liner comprises silicon carbonitride (¶ [0064]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught by Chung with the liner material taught by Bae since it has been held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960), and MPEP 2144.07 Art Recognized Suitability for an Intended Purpose.
Regarding claim 7, Chung as modified teaches the semiconductor device of claim 1.
Chung as modified does not teach wherein the second capping layer material comprises silicon oxycarbonitride.
FIG. 2 of Bae teaches a transistor device comprising: a gate electrode (110 ¶ [0034]) and a second capping layer material (113) over the gate electrode (110 ¶ [0034]), wherein the second capping layer material comprises silicon oxycarbonitride (¶ [0064]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught by Chung with the second capping layer material taught by Bae since it has been held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960), and MPEP 2144.07 Art Recognized Suitability for an Intended Purpose.
Regarding claim 13, Chung as modified teaches the semiconductor device of claim 8.
Chung as modified does not teach wherein the void-free gate mask material comprises silicon oxycarbonitride.
FIG. 2 of Bae teaches a transistor device comprising: a gate electrode (110 ¶ [0034]) and a gate mask material (113) over the gate electrode (110 ¶ [0034]), wherein the gate mask material comprises silicon oxycarbonitride (¶ [0064]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught by Chung with the gate mask material taught by Bae since it has been held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960), and MPEP 2144.07 Art Recognized Suitability for an Intended Purpose.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Chung in view of Tsai, and further in view of Chang et al. (US 20180151745 A1; hereinafter Chang)
Regarding claim 12, Chung as modified teaches the semiconductor device of claim 8.
Chung as modified does not teach wherein the first liner has a thickness of between about 2 nm and about 6 nm.
FIG. of Chang teaches a first liner (125 ¶ [0091]) over a gate electrode (110 ¶ [0083]), wherein the first liner (125) has a thickness of between about 2 nm and about 6 nm (e.g. 0.5 nm to 10 nm ¶ [0094]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught by Chung with the thickness of the liner layer taught by Chang since it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969), wherein in the instant case the thickness of the first liner determines the resulting device dimensions making it a result effective variable, In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), and MPEP 2144.05 Obviousness of Ranges II. OPTIMIZATION OF RANGES A. Optimization Within Prior Art Conditions or Through Routine Experimentation B. Only Result-Effective Variables Can Be Optimized.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Chung in view of Tsai, and further in view of Tang et al. (US 10002933 B1; hereinafter Tang).
Regarding claim 14, Chung as modified teaches the semiconductor device of claim 8.
Chung as modified does not teach wherein the void-free gate mask material comprises SiCO.
FIG. 1K of Tang teaches a transistor device comprising a gate mask material (134 col. 5/lines 17-24) over a gate electrode (124 col. 4/lines 6-11), wherein the gate mask material comprises SiCO (col. 5/lines 32-35).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught by Chung with the gate mask material taught by Tang since it has been held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960), and MPEP 2144.07 Art Recognized Suitability for an Intended Purpose.
Allowable Subject Matter
Claims 5-6, 9, and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 5 recites the semiconductor device of claim 1, wherein the first liner comprises hafnium oxide.
Chung in view of Tsai teaches the semiconductor device of claim 1.
However, the prior art fails to teach or reasonably suggest “wherein the first liner comprises hafnium oxide” together with all the limitations of claims 1 and 5 as claimed. Claim 6 contains allowable subject matter insofar as it depends upon and requires all the limitations of claims 1 and 5.
Claim 9 recites the semiconductor device of claim 8, wherein the first liner is a first material and the second liner is a second material different from the first material.
Chung in view of Tsai teaches the semiconductor device of claim 8.
However, the prior art fails to teach or reasonably suggest “wherein the first liner is a first material and the second liner is a second material different from the first material” together with all the limitations of claims 8 and 9 as claimed.
Claim 11 recites the semiconductor device of claim 8, wherein the first liner is hafnium oxide.
Chung in view of Tsai teach the semiconductor device of claim 8.
However, the prior art fails to teach or reasonably suggest “wherein the first liner is hafnium oxide” together with all the limitations of claims 8 and 11 as claimed.
Claims 15-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 15, FIGS. 4-6 of Chung teach a semiconductor device (e.g. FIG. 6) comprising: a first capping layer (146) over a gate electrode (130/1140), the gate electrode (130/1140) being located in a trench (trench of 180) located over a semiconductor fin (110); and a capping layer material (145) located over the first capping layer (146) in the trench (trench of 180); and a crystalline first liner (1135a) located between the capping layer material (145) and the first capping layer (146, e.g. between an upper portion of 145 and 146); and wherein the crystalline first liner (1135a) and the crystalline second liner (1135b) collectively surround a portion of the capping layer material (1131b).
However, the prior art fails to teach or reasonably suggest “a crystalline second liner on an opposite side of the capping layer material from the crystalline first liner” together with all the limitations of claim 15 as claimed. Claims 16-20 are allowable insofar as they depend upon and require all the limitations of claim 15.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nora T Nix whose telephone number is (571)270-1972. The examiner can normally be reached Monday - Friday 9:00 am - 5:00 pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Nora T. Nix/Assistant Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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