DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kishishita(USPGPUB DOCUMENT: 20190074297, hereinafter Kishishita) in view of Nelson (USPGPUB DOCUMENT: 2019/0355756, hereinafter Nelson).
Re claim 1 Kishishita discloses in Fig 1, 2, 14 a semiconductor device, comprising: a first power supply line(VDD/41/43)[0052,0078,0123]; a first field effect transistor (FET(P1/P2/N1/N2)); a second FET(P1/P2/N1/N2); wherein the first power supply line(VDD/41/43)[0052,0078,0123], first FET(P1/P2/N1/N2), second FET(P1/P2/N1/N2), and second power supply are arranged in order along a first direction, and the first FET(P1/P2/N1/N2) and the second FET(P1/P2/N1/N2) share a gate(32/31)[0043].
Kishishita does not discloses a second power supply line, wherein the first power supply line(VDD/41/43)[0052,0078,0123], first FET(P1/P2/N1/N2), second FET(P1/P2/N1/N2), and second power supply are arranged in order along a first direction,
Nelson discloses a second power supply line(Vdd/Vss of Nelson),
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Nelson to the teachings of Kishishita in order to save area [0026, Nelson]. In doing so, a second power supply line(Vdd/Vss of Nelson), wherein the first power supply line(VDD/41/43)[0052,0078,0123], first FET(P1/P2/N1/N2), second FET(P1/P2/N1/N2), and second power supply(Vdd/Vss of Nelson) are arranged in order along a first direction,
Re claim 2 Kishishita and Nelson disclose the semiconductor device of claim 1, wherein the first power supply line(VDD/41/43)[0052,0078,0123] is coupled to a first FET(P1/P2/N1/N2) drain contact through a first via contact.
Re claim 3 Kishishita and Nelson disclose the semiconductor device of claim 2, wherein the second power supply line is coupled to a second FET(P1/P2/N1/N2) source contact through a second via contact.
Re claim 4 Kishishita and Nelson disclose the semiconductor device of claim 3, further comprising a signal line adjacent to the second power supply line and coupled to a second FET(P1/P2/N1/N2) drain contact through a third via contact.
Re claim 5 Kishishita and Nelson disclose the semiconductor device of claim 1, wherein the first power supply line(VDD/41/43)[0052,0078,0123] is coupled to a first FET(P1/P2/N1/N2) source contact through a first via contact.
Re claim 6 Kishishita and Nelson disclose the semiconductor device of claim 5, wherein the second power supply line located is coupled to a second FET(P1/P2/N1/N2) drain contact through a second via contact.
Re claim 7 Kishishita and Nelson disclose the semiconductor device of claim 6, further comprising a signal line adjacent to the second power supply line and coupled to a second FET(P1/P2/N1/N2) source contact through a third via contact.
Re claim 8 Kishishita and Nelson disclose the semiconductor device of claim 1, wherein: the first FET(P1/P2/N1/N2) is a p-type FET(P1/P2/N1/N2), and the second FET(P1/P2/N1/N2) is an n-type FET(P1/P2/N1/N2).
Re claim 9 Kishishita and Nelson disclose the semiconductor device of claim 8, wherein the second power supply line supplies a lower potential than the first power supply line(VDD/41/43)[0052,0078,0123].
Re claim 10 Kishishita and Nelson disclose the semiconductor device of claim 1, wherein the first FET(P1/P2/N1/N2) is an n-type FET(P1/P2/N1/N2), and the second FET(P1/P2/N1/N2) is a p-type FET(P1/P2/N1/N2).
Re claim 11 Kishishita and Nelson disclose the semiconductor device of claim 10, wherein the second power supply line supplies a higher potential than the first power supply line(VDD/41/43)[0052,0078,0123].
Re claim 12 Kishishita and Nelson disclose the semiconductor device of claim 1, further comprising a signal line adjacent the second power supply line and coupled to the gate(32/31)[0043].
Re claim 13 Kishishita discloses in Fig 1, 2, 14 a semiconductor device, comprising: a first power supply line(VDD/41/43)[0052,0078,0123]; a first gate-all-around field effect transistor (GAA FET(P1/P2/N1/N2)); a second GAA FET(P1/P2/N1/N2); wherein the first power supply line(VDD/41/43)[0052,0078,0123], first GAA FET(P1/P2/N1/N2), second GAA FET(P1/P2/N1/N2), are arranged in order along a first direction, the first power supply line(VDD/41/43)[0052,0078,0123] extend in a second direction crossing the first direction, and the first GAA FET(P1/P2/N1/N2) and the second GAA FET(P1/P2/N1/N2) share a gate(32/31)[0043].
Kishishita does not discloses a second power supply line, wherein the first power supply line(VDD/41/43)[0052,0078,0123], first GAA FET(P1/P2/N1/N2), second GAA FET(P1/P2/N1/N2), and second power supply are arranged in order along a first direction, the first power supply line(VDD/41/43)[0052,0078,0123] and the second power supply line extend in a second direction crossing the first direction,
Nelson discloses a second power supply line(Vdd/Vss of Nelson),
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Nelson to the teachings of Kishishita in order to save area [0026, Nelson]. In doing so, a second power supply line(Vdd/Vss of Nelson), wherein the first power supply line(VDD/41/43)[0052,0078,0123], first GAA FET(P1/P2/N1/N2), second GAA FET(P1/P2/N1/N2), and second power supply(Vdd/Vss of Nelson) are arranged in order along a first direction, the first power supply line(VDD/41/43)[0052,0078,0123] and the second power supply line(Vdd/Vss of Nelson) extend in a second direction crossing the first direction,
Re claim 14 Kishishita and Nelson disclose the semiconductor device of claim 13, further comprising a bar contact disposed between the first GAA FET(P1/P2/N1/N2) and the second GAA FET(P1/P2/N1/N2).
Re claim 15 Kishishita and Nelson disclose the semiconductor device of claim 13, wherein the first power supply line(VDD/41/43)[0052,0078,0123] is coupled to a first GAA FET(P1/P2/N1/N2) drain contact through a first via contact.
Re claim 16 Kishishita and Nelson disclose the semiconductor device of claim 15, wherein the second power supply line is coupled to a second GAA FET(P1/P2/N1/N2) source contact through a second via contact.
Re claim 17 Kishishita discloses in Fig 1, 2, 14 a semiconductor device, comprising: a first gate-all-around field effect transistor (GAA FET(P1/P2/N1/N2)) disposed over a substrate[0041]; a second GAA FET(P1/P2/N1/N2) disposed over the substrate[0041]; a first power supply line(VDD/41/43)[0052,0078,0123] coupled to the first GAA FET(P1/P2/N1/N2); wherein the first GAA FET(P1/P2/N1/N2) comprises a gate(32/31)[0043] electrode and source and drain regions(25/26/27/28)[0076] on opposing sides of the gate(32/31)[0043] structure, the first power supply line(VDD/41/43)[0052,0078,0123] is buried in an isolation insulating layer(146c/146a/146b), the first power supply line(VDD/41/43)[0052,0078,0123] is coupled to either the source region or the drain region, and the first power supply line(VDD/41/43)[0052,0078,0123] is isolated from the gate(32/31)[0043] electrode by an insulating layer(146c/146a/146b).
Kishishita does not discloses a second power supply line coupled to the second GAA FET, wherein the first GAA FET(P1/P2/N1/N2) comprises a gate(32/31)[0043] electrode disposed over a pair of fin bottom structures and source and drain regions(25/26/27/28)[0076] disposed over the pair of fin bottom structures on opposing sides of the gate(32/31)[0043] structure, the first power supply line(VDD/41/43)[0052,0078,0123] is buried in an isolation insulating layer(146c/146a/146b) between the two fin bottom structures,
Nelson discloses a second power supply line(Vdd/Vss of Nelson), a pair of fin bottom structures(130/430 of Nelson)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Nelson to the teachings of Kishishita in order to save area [0026, Nelson]. In doing so, a second power supply line(Vdd/Vss of Nelson) coupled to the second GAA FET, wherein the first GAA FET(P1/P2/N1/N2) comprises a gate(32/31)[0043] electrode disposed over a pair of fin bottom structures(130/430 of Nelson) and source and drain regions(25/26/27/28)[0076] disposed over the pair of fin bottom structures(130/430 of Nelson) on opposing sides of the gate(32/31)[0043] structure, the first power supply line(VDD/41/43)[0052,0078,0123] is buried in an isolation insulating layer(146c/146a/146b) between the two fin bottom structures(130/430 of Nelson),
Re claim 18 Kishishita and Nelson disclose the semiconductor device of claim 17, wherein: the first GAA FET(P1/P2/N1/N2) is a p-type FET(P1/P2/N1/N2), and the second GAA FET(P1/P2/N1/N2) is an n-type FET(P1/P2/N1/N2).
Re claim 19 Kishishita and Nelson disclose the semiconductor device of claim 18, wherein the second power supply line supplies a lower potential than the first power supply line(VDD/41/43)[0052,0078,0123].
Re claim 20 Kishishita and Nelson disclose the semiconductor device of claim 17, wherein the first FET(P1/P2/N1/N2) is an n-type FET(P1/P2/N1/N2), and the second FET(P1/P2/N1/N2) is a p-type FET(P1/P2/N1/N2), and the second power supply line supplies a higher potential than the first power supply line(VDD/41/43)[0052,0078,0123].
Conclusion
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
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