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The information disclosure statement (IDS) submitted on 7/12/2024, 9/10/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
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Claims 1-7, 9-16, 18 and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-4, 7, 10, 12 and 14 of U.S. Patent No. 12,080,766 in view of Liao (US 2022/0165885).
Regarding claim 1, Pat '766 discloses, in claim 1, a semiconductor device structure, comprising:
a dielectric layer disposed over the semiconductor layer; a conductive feature over the dielectric layer; and a doped semiconductor feature extending through the semiconductor layer and the dielectric layer to interface the first source/drain feature and the conductive feature ("a dielectric layer over the semiconductor layer; a doped semiconductor feature extending through the semiconductor layer and the dielectric layer to be in contact with the source feature; and a metal contact plug over the doped semiconductor feature, wherein the doped semiconductor feature partially extends into the metal contact plug", in claim 1 of Pat '766, is interpreted as the same limitation).
Pat '766 does not explicitly disclose a first active region and a second active region; a first source/drain feature extending between the first active region and the second active region; a first gate structure engaging the first active region; a second gate structure engaging the second active region; a semiconductor layer disposed over and engaging the first gate structure and the second gate structure.
Liao teaches, in at least figures 14B, 21, and related text, the device comprising a first active region (center transistor region, figures) and a second active region (right transistor region, figure 14B); a first source/drain feature (92, [25]) extending between the first active region (center transistor region, figures) and the second active region (right transistor region, figure 14B); a first gate structure (102/104 of center transistor, [15], figures) engaging the first active region (center transistor region, figures); a second gate structure (102/104 of right transistor, [15], figure 14B) engaging the second active region (right transistor region, figure 14B); a semiconductor layer (54, [14], [19]) disposed over and engaging the first gate structure (102/104 of center transistor, [15], figures) and the second gate structure (102/104 of right transistor, [15], figure 14B), for the purpose of providing conductive vias are formed through the device layer, connecting the conductive features of the back-side interconnect structure ([12]) thereby improving integration of density.
Pat '766 and Liao are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '766 with the specified features of Liao because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '766 to have the first active region and the second active region; the first source/drain feature extending between the first active region and the second active region; the first gate structure engaging the first active region; the second gate structure engaging the second active region; the semiconductor layer disposed over and engaging the first gate structure and the second gate structure, as taught by Liao, for the purpose of providing conductive vias are formed through the device layer, connecting the conductive features of the back-side interconnect structure ([12], Liao) thereby improving integration of density.
Regarding claim 2, Pat '766 in view of Liao discloses the semiconductor device structure of claim 1 as described above.
Liao further teaches, in at least figures 14B, 21, and related text, the first active region (center transistor region, figures) comprises a first plurality of nanostructures (68 (56B), [26], [40]), wherein the second active region (right transistor region, figure 14B) comprises a second plurality of nanostructures (68 (56B), [26], [40]), for the purpose of providing conductive vias are formed through the device layer, connecting the conductive features of the back-side interconnect structure ([12]) thereby improving integration of density.
Regarding claim 3, Pat '766 in view of Liao discloses the semiconductor device structure of claim 2 as described above.
Liao further teaches, in at least figures 14B, 21, and related text, the first gate structure (102/104 of center transistor, [15], figures) wraps around each of the first plurality of nanostructures (68 (56B), [26], [40]), wherein the second gate structure (102/104 of right transistor, [15], figure 14B) wraps around each of the second plurality of nanostructures (68 (56B), [26], [40]), for the purpose of providing conductive vias are formed through the device layer, connecting the conductive features of the back-side interconnect structure ([12]) thereby improving integration of density.
Regarding claim 4, Pat '766 in view of Liao discloses the semiconductor device structure of claim 2 as described above.
Liao further teaches, in at least figures 14B, 21, and related text, a first plurality of inner spacer features (84, [45]) interleaving the first plurality of nanostructures (68 (56B), [26], [40]); and a second plurality of inner spacer features (84, [45]) interleaving the second plurality of nanostructures (68 (56B), [26], [40]), for the purpose of providing conductive vias are formed through the device layer, connecting the conductive features of the back-side interconnect structure ([12]) thereby improving integration of density.
Regarding claim 5, Pat '766 in view of Liao discloses the semiconductor device structure of claim 4 as described above.
Liao further teaches, in at least figures 14B, 21, and related text, the first gate structure (102/104 of center transistor, [15], figures) is spaced apart from the first source/drain feature (92, [25]) by the first plurality of inner spacer features (84, [45]), wherein the second gate structure (102/104 of right transistor, [15], figure 14B) is spaced apart from the first source/drain feature (92, [25]) by the second plurality of inner spacer features (84, [45]), for the purpose of providing conductive vias are formed through the device layer, connecting the conductive features of the back-side interconnect structure ([12]) thereby improving integration of density.
Regarding claim 6, Pat '766 in view of Liao discloses the semiconductor device structure of claim 4 as described above.
Liao further teaches, in at least figures 14B, 21, and related text, at least one of the first plurality of inner spacer features (84, [45]) and at least one of the second plurality of inner spacer features (84, [45]) interface the semiconductor layer (54, [14], [19]), for the purpose of providing conductive vias are formed through the device layer, connecting the conductive features of the back-side interconnect structure ([12]) thereby improving integration of density.
Regarding claim 7, Pat '766 in view of Liao discloses the semiconductor device structure of claim 1 as described above.
Pat '766 further discloses, in claims 2 and 3, the semiconductor layer comprises silicon, wherein the dielectric layer comprises silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, or zirconium oxide (all limitations are the same with the limitations recited in claims 2 and 3 of Pat '766).
Regarding claim 9, Pat '766 in view of Liao discloses the semiconductor device structure of claim 1 as described above.
Pat '766 further discloses, in claim 1, the doped semiconductor feature partially extends into the conductive feature ("the doped semiconductor feature partially extends into the metal contact plug", in claim 1 of Pat '766, is interpreted as the same limitation).
Regarding claim 10, Pat '766 in view of Liao discloses the semiconductor device structure of claim 1 as described above.
Pat '766 further discloses, in claim 4, a silicide layer disposed at an interface between the doped semiconductor feature and the conductive feature (“a silicide layer disposed at an interface between the doped semiconductor feature and the metal contact plug", in claim 4 of Pat '766, is interpreted as the same limitation).
Regarding claim 11, Pat '766 in view of Liao discloses the semiconductor device structure of claim 1 as described above.
Liao further teaches, in at least figures 14B, 21, and related text, a second source/drain feature (92P, [73]) such that the first active region (center transistor region, figures) is sandwiched between the first source/drain feature (92, [25]) and the second source/drain feature (92P, [73]), for the purpose of providing conductive vias are formed through the device layer, connecting the conductive features of the back-side interconnect structure ([12]) thereby improving integration of density.
Pat '766 further discloses, in claim 7, an interlayer dielectric layer extending through the dielectric layer and the semiconductor layer to partially extending into the second source/drain feature (“a portion of the ILD layer also penetrates the dielectric layer and the semiconductor layer to partially extends into the drain feature ", in claim 7 of Pat '766, is interpreted as the same limitation).
Regarding claim 12, Pat '766 discloses, in claims 10, 12 and 14, a semiconductor structure, comprising:
a source feature and a drain feature; a plurality of nanostructures sandwiched between the source feature and the drain feature along a direction; a plurality of inner spacer features interleaving the plurality of nanostructures; a gate structure wrapping around each of the plurality of nanostructures; a dielectric layer disposed over the silicon layer (all limitations are the same with the limitations recited in claim 10 of Pat '766);
a first conductive feature over the dielectric layer ("a metal contact feature disposed over the dielectric layer and the epitaxial extension feature", in claim 14 of Pat '766, is interpreted as the same limitation); and
a second conductive feature extending through the silicon layer and the dielectric layer to electrically couple the source feature ("an epitaxial extension feature arising from a top surface of the source feature and extending through the silicon layer and the dielectric layer" and “the source feature, the drain feature, and the epitaxial extension feature comprise silicon and an n- type dopant”, in claims 1 and 12 of Pat '766, are interpreted as the same limitation).
Pat '766 does not explicitly disclose a silicon layer disposed over and engaging the gate structure and a topmost one of the plurality of inner spacer features; a second conductive feature extending through the silicon layer and the dielectric layer to electrically couple the source feature and the first conductive feature, wherein the second conductive feature partially extends into the first conductive feature.
Pat '766 teaches, in claim 1, a second conductive feature extending through the silicon layer and the dielectric layer to electrically couple the source feature and the first conductive feature, wherein the second conductive feature partially extends into the first conductive feature ("a doped semiconductor feature extending through the semiconductor layer and the dielectric layer to be in contact with the source feature; and a metal contact plug over the doped semiconductor feature, wherein the doped semiconductor feature partially extends into the metal contact plug", in claim 1 of Pat '766, is interpreted as the same limitation), for the purpose of providing epitaxial extension feature that increase an interface area between the backside source contact and the source feature.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in claim 10 of Pat '766 to have the second conductive feature extending through the silicon layer and the dielectric layer to electrically couple the source feature and the first conductive feature, wherein the second conductive feature partially extends into the first conductive feature, as taught by claim 1 of Pat '766, for the purpose of providing epitaxial extension feature that increase an interface area between the backside source contact and the source feature.
Liao teaches, in at least figures 14B, 21, and related text, the device comprising a silicon layer (54, [14], [19]) disposed over and engaging the gate structure (102/104 of center transistor, [15], figures) and a topmost one of the plurality of inner spacer features (84, [45]), for the purpose of providing conductive vias are formed through the device layer, connecting the conductive features of the back-side interconnect structure ([12]) thereby improving integration of density.
Pat '766 and Liao are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '766 with the specified features of Liao because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '766 to have the silicon layer disposed over and engaging the gate structure and a topmost one of the plurality of inner spacer features, as taught by Liao, for the purpose of providing conductive vias are formed through the device layer, connecting the conductive features of the back-side interconnect structure ([12], Liao) thereby improving integration of density.
Regarding claim 13, Pat '766 in view of Liao discloses the semiconductor structure of claim 12 as described above.
Liao further teaches, in at least figures 14B, 21, and related text, the first conductive feature (112C, [89]) comprises aluminum (Al) ([89]), rhodium (Rh), ruthenium (Ru) ([89]), copper (Cu) ([89]), iridium (Ir), or tungsten (W) ([89]), for the purpose of providing conductive vias are formed through the device layer, connecting the conductive features of the back-side interconnect structure ([12]) thereby improving integration of density.
Regarding claim 14, Pat '766 in view of Liao discloses the semiconductor structure of claim 13 as described above.
Pat '766 further discloses, in claim 12, the second conductive feature comprises silicon and an n-type dopant ("the source feature, the drain feature, and the epitaxial extension feature comprise silicon and an n- type dopant", in claim 12 of Pat '766, is interpreted as the same limitation).
Regarding claim 15, Pat '766 in view of Liao discloses the semiconductor structure of claim 14 as described above.
Pat '766 does not explicitly disclose a silicide layer at an interface between the first conductive feature and the second conductive feature.
Pat '766 teaches, in claim 4, a silicide layer at an interface between the first conductive feature and the second conductive feature ("a silicide layer disposed at an interface between the doped semiconductor feature and the metal contact plug ", in claim 4 of Pat '766, is interpreted as the same limitation), for the purpose of providing epitaxial extension feature that increase an interface area between the backside source contact and the source feature.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in claim 10 of Pat '766 to have the silicide layer at an interface between the first conductive feature and the second conductive feature, as taught by claim 4 of Pat '766, for the purpose of providing epitaxial extension feature that increase an interface area between the backside source contact and the source feature.
Liao further teaches, in at least figures 14B, 21, and related text, the silicide layer (138, [88]) comprises titanium silicide (TiSi) ([88]), titanium silicon nitride (TiSiN), tantalum silicide (TaSi), tungsten silicide (WSi), cobalt silicide (CoSi) ([88]), or nickel silicide (NiSi) ([88]), for the purpose of providing conductive vias are formed through the device layer, connecting the conductive features of the back-side interconnect structure ([12]) thereby improving integration of density.
Regarding claim 16, Pat '766 in view of Liao discloses the semiconductor structure of claim 13 as described above.
Pat '766 further discloses, in claim 14, an interlayer dielectric layer disposed over the dielectric layer; and a dielectric liner spacing the interlayer dielectric layer from the first conductive feature ("an etch stop layer (ESL) disposed on the dielectric layer; an interlayer dielectric (ILD) layer over the ESL; and a metal contact feature disposed over the dielectric layer and the epitaxial extension feature, wherein the metal contact feature is disposed in the ESL and the ILD layer such that sidewalls of the metal contact feature are in contact with sidewalls of the ESL and the ILD layer", in claim 14 of Pat '766, is interpreted as the same limitation).
Pat '766 does not explicitly disclose the interlayer dielectric layer extends through the dielectric layer and the silicon layer to interface the drain feature.
Pat '766 teaches, in claim 7, the interlayer dielectric layer extends through the dielectric layer and the silicon layer to interface the drain feature ("a portion of the ILD layer also penetrates the dielectric layer and the semiconductor layer to partially extends into the drain feature ", in claim 7 of Pat '766, is interpreted as the same limitation), for the purpose of providing epitaxial extension feature that increase an interface area between the backside source contact and the source feature.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in claim 10 of Pat '766 to have the interlayer dielectric layer extending through the dielectric layer and the silicon layer to interface the drain feature, as taught by claim 7 of Pat '766, for the purpose of providing epitaxial extension feature that increase an interface area between the backside source contact and the source feature.
Regarding claim 18, Pat '766 discloses, in claims 10, 12 and 14, a semiconductor structure, comprising:
a source feature and a drain feature; a plurality of nanostructures sandwiched between the source feature and the drain feature along a direction; a plurality of inner spacer features interleaving the plurality of nanostructures; a gate structure wrapping around each of the plurality of nanostructures; a dielectric layer disposed over the silicon layer (all limitations are the same with the limitations recited in claim 10 of Pat '766);
a first conductive feature over the dielectric layer ("a metal contact feature disposed over the dielectric layer and the epitaxial extension feature", in claim 14 of Pat '766, is interpreted as the same limitation); and
a second conductive feature extending through the silicon layer and the dielectric layer to electrically couple the source feature, wherein the second conductive feature comprises silicon and an n-type dopant ("an epitaxial extension feature arising from a top surface of the source feature and extending through the silicon layer and the dielectric layer" and “the source feature, the drain feature, and the epitaxial extension feature comprise silicon and an n- type dopant”, in claims 1 and 12 of Pat '766, are interpreted as the same limitation).
Pat '766 does not explicitly disclose a silicon layer disposed over and engaging the gate structure and a topmost one of the plurality of inner spacer features; the first conductive feature comprises aluminum (Al), rhodium (Rh), ruthenium (Ru), copper (Cu), iridium (Ir), or tungsten (W); a second conductive feature extending through the silicon layer and the dielectric layer to electrically couple the source feature and the first conductive feature.
Pat '766 teaches, in claim 1, a second conductive feature extending through the silicon layer and the dielectric layer to electrically couple the source feature and the first conductive feature ("a doped semiconductor feature extending through the semiconductor layer and the dielectric layer to be in contact with the source feature; and a metal contact plug over the doped semiconductor feature, wherein the doped semiconductor feature partially extends into the metal contact plug", in claim 1 of Pat '766, is interpreted as the same limitation), for the purpose of providing epitaxial extension feature that increase an interface area between the backside source contact and the source feature.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in claim 10 of Pat '766 to have the second conductive feature extending through the silicon layer and the dielectric layer to electrically couple the source feature and the first conductive feature, as taught by claim 1 of Pat '766, for the purpose of providing epitaxial extension feature that increase an interface area between the backside source contact and the source feature.
Liao teaches, in at least figures 14B, 21, and related text, the device comprising a silicon layer (54, [14], [19]) disposed over and engaging the gate structure (102/104 of center transistor, [15], figures) and a topmost one of the plurality of inner spacer features (84, [45]); the first conductive feature (112C, [89]) comprises aluminum (Al) ([89]), rhodium (Rh), ruthenium (Ru) ([89]), copper (Cu) ([89]), iridium (Ir), or tungsten (W) ([89]), for the purpose of providing conductive vias are formed through the device layer, connecting the conductive features of the back-side interconnect structure ([12]) thereby improving integration of density.
Pat '766 and Liao are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '766 with the specified features of Liao because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '766 to have the silicon layer disposed over and engaging the gate structure and a topmost one of the plurality of inner spacer features; the first conductive feature comprising aluminum (Al), rhodium (Rh), ruthenium (Ru), copper (Cu), iridium (Ir), or tungsten (W), as taught by Liao, for the purpose of providing conductive vias are formed through the device layer, connecting the conductive features of the back-side interconnect structure ([12], Liao) thereby improving integration of density.
Regarding claim 20, Pat '766 in view of Liao discloses the semiconductor structure of claim 18 as described above.
Pat '766 further discloses, in claim 4, a silicide layer at an interface between the first conductive feature and the second conductive feature ("a silicide layer disposed at an interface between the doped semiconductor feature and the metal contact plug ", in claim 4 of Pat '766, is interpreted as the same limitation).
Liao further teaches, in at least figures 14B, 21, and related text, the silicide layer (138, [88]) comprises titanium silicide (TiSi) ([88]), titanium silicon nitride (TiSiN), tantalum silicide (TaSi), tungsten silicide (WSi), cobalt silicide (CoSi) ([88]), or nickel silicide (NiSi) ([88]), for the purpose of providing conductive vias are formed through the device layer, connecting the conductive features of the back-side interconnect structure ([12]) thereby improving integration of density.
Allowable Subject Matter
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1 and 8 that recite "the doped semiconductor feature partially extends into the first source/drain feature" in combination with other elements of the base claims 1 and 8.
Claim 17 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 12, 13, 16, and 17 that recite "the dielectric liner comprises silicon nitride" in combination with other elements of the base claims 12, 13, 16, and 17.
Claim 19 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 18 and 19 that recite "the second conductive feature partially extends into the first conductive feature and the source feature" in combination with other elements of the base claims 18 and 19.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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/TONG-HO KIM/ Primary Examiner, Art Unit 2811
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