DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/12/2024 was filed after the mailing date of the application. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claims 1-20 are pending.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-16 of U.S. Patent No. 11,908,838. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-16 of ‘838 disclose all limitations cited in claims 1-20 of present application.
Regarding claim 1, Claim 1 of ‘838 discloses a three-dimensional device structure comprising:
a first die comprising a first semiconductor substrate,
a second die disposed on the first die and comprising a second semiconductor substrate,
a dielectric encapsulation (DE) layer disposed on the first die and surrounding the second die,
a redistribution layer structure disposed on the second die and the DE layer, and
a deep trench capacitor (DTC) embedded in the DE layer and electrically connected to the first die and the redistribution layer structure (lines 34-50, Col. 11).
Regarding claim 2, Claim 1 of ‘838 discloses the structure of claim 1 wherein the DTC is disposed in a trench formed in the DE layer (lines 42-43, Col.11).
Regarding claim 3, Claim 1 of ‘838 discloses wherein the DTC comprises:
a first conductive layer electrically connected to the first die,
a second conductive layer electrically connected to the redistribution layer structure, and
a first dielectric layer disposed between the first conductive layer and the second conductive layer (lines 45-51, Col. 11).
Regarding claim 4, Claim 2 of ‘838 discloses wherein the DTC comprises a second dielectric layer surrounded by the second conductive layer (lines 52-54, Col. 11).
Regarding claim 5, Claim 3 of ‘838 discloses wherein the DTC comprises a contact flange comprising end regions of the first conductive layer, first dielectric layer, and second conductive layer that are disposed on an upper surface of the DE layer, and the redistribution layer structure comprises a metal feature that electrically contacts the end region of the second conductive layer (lines 55-63, Col. 11).
Regarding claim 6, Claim 4 of ‘838 discloses wherein the redistribution layer structure comprises metal features embedded in a dielectric layer, and one of the metal features electrically contacts the second conductive layer (lines 64-67, Col. 11; lines 1-2, Col. 12).
Regarding claim 7, Claim 5 of ‘838 discloses further comprising a through dielectric via (TDV) structure extending from an upper surface of the first die through the DE layer to electrically connect the first die and the redistribution layer structure (lines 3-7, Col. 12).
Regarding claim 8, Claim 6 of ‘838 discloses wherein the DTC is disposed between the TDV structure and the second die (lines 8-10, Col. 12).
Regarding claim 9, Claim 7 of ‘838 discloses further comprising multiple DTCs disposed in trenches formed in the DE layer (lines 11-14, Col. 12).
Regarding claim 10, Claim 8 of ‘838 discloses wherein the first die further comprises a first interconnect structure disposed on the first semiconductor substrate, and the second die further comprises a second interconnect structure disposed on the second semiconductor substrate and electrically connected to the first interconnect structure (lines 15-22, Col. 12).
Regarding claim 11, Claim 9 of ‘838 discloses a three-dimensional device structure comprising:
a first die comprising a first semiconductor substrate,
second dies disposed on and electrically connected to the first die, each of the second dies comprising a respective second substrate,
a dielectric encapsulation DE layer disposed on the first die and surround the second dies,
a redistribution layer structure disposed on the second dies and the DE layer,
through dielectric via (TDV) structures extending from an upper surface of the first die through the DE layer to electrically connect the first die and the redistribution layer structure, and
deep trench capacitors DTCs embedded in the DE layer and electrically connected to the first die and the redistribution layer structure, wherein the DTCs are each disposed between one of the TDV structures and an adjacent one of the second dies (lines 23-40, Col. 12).
Regarding claim 12, Claim 9 of ‘838 discloses wherein the DTCs are disposed in respective trenches formed in the DE layer (lines 36-37, Col. 12).
Regarding claim 13, Claim 9 of ‘838 discloses wherein each DTC comprises: a first conductive layer electrically connected to the first die, a second conductive layer electrically connected to the redistribution layer structure, and a first dielectric layer disposed between the first conductive layer and the second conductive layer (lines 42-48, Col. 12).
Regarding claim 14, Claim 10 of ‘838 discloses wherein each DTC comprises a second dielectric layer surrounded by the second conductive layer (lines 48-50, Col. 12).
Regarding claim 15, Claim 11 of ‘838 discloses wherein:
each DTC comprises a contact flange comprising end regions of the first conductive layer, first dielectric layer, and second conductive layer that are disposed on an upper surface of the DE layer, and the redistribution layer structure comprises metal features that electrically contact the end regions of the second conductive layers of the DTCs (lines 51-59, Col. 12).
Regarding claim 16, Claim 12 of ‘838 discloses wherein the redistribution layer structure comprises metal features embedded in a dielectric layer and electrically contacting the second conductive layers (lines 60-64, Col. 12).
Regarding claim 17, Claim 13 of ‘838 discloses wherein the first die further comprises a first interconnect structure disposed on the first semiconductor substrate, and
each of the second dies further comprises second interconnect structures disposed on the second semiconductor substrate and electrically connected to the first interconnect structure (lines 64-67, Col. 12; lines 1-4, Col. 13).
Regarding claim 18, Claim 14 of ‘838 discloses a three-dimensional structure comprising:
a first die comprising a first semiconductor substrate and a first interconnect structure electrically connected to a device layer of the first semiconductor substrate,
a dielectric encapsulation DE layer disposed on the first die,
a redistribution layer structure disposed on the DE layer,
a deep trench capacitor DTC embedded in the DE layer and electrically connected to the first interconnect structure and the redistribution layer structure (lines 5-15, Col. 13).
Regarding claim 19, Claim 14 of ‘838 discloses wherein the DTC comprises:
a first conductive layer electrically connected to the first die,
a second conductive layer electrically connected to the redistribution layer structure, and
a first dielectric layer disposed between the first conductive layer and the second conductive layer (lines 20-25, Col. 13).
Regarding claim 20, Claim 16 of ‘838 discloses further comprising:
a second die disposed on the first die and embedded in the DE layer,
a through dielectric via DTV structure embedded in the DE layer and electrically connected to the first die and the redistribution layer structure,
wherein the DTC is disposed between the TDV structure and the second die (lines 1-6, Col. 14).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THAO P LE whose telephone number is (571)272-1785. The examiner can normally be reached on Monday-Friday 9AM-6PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
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/THAO P LE/Primary Examiner, Art Unit 2818
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