DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 12, and 18 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims 2-11, 13-17, 19-20 are rejected as they include the limitations of claims 1, 12, or 18 on which they depend.
Claim 1 recites the limitation, “source/drain feature,” in lines 3-5, 7 of the claim. The meets and bounds of the phrase, “source/drain feature,” are unclear, as it is unclear whether this phrase means a source/drain region itself or a separate feature, which is not the source/drain but instead is formed in proximity to the source/drain. The specification discloses features formed in a source/drain region (para. 27: el. 128) and discloses features formed adjacent to these epitaxial features 128 (para. 28, 34: el. 130, 132, 146), but does not provide clarity on the meaning of the phrase, “source/drain feature,” or clarity on which features or structures are associated with the meaning of the phrase. For the purpose of this office action, the limitation is interpreted to have the following meaning: the source/drain region.
Claim 12 recites the limitation, “source/drain feature,” in lines 4, 6-7, 9 of the claim. The meets and bounds of the phrase, “source/drain feature,” are unclear, as it is unclear whether this phrase means a source/drain region itself or a separate feature, which is not the source/drain but instead is formed in proximity to the source/drain. The specification discloses features formed in a source/drain region (para. 27: el. 128) and discloses features formed adjacent to these epitaxial features 128 (para. 28, 34: el. 130, 132, 146), but does not provide clarity on the meaning of the phrase, “source/drain feature,” or clarity on which features or structures are associated with the meaning of the phrase. For the purpose of this office action, the limitation is interpreted to have the following meaning: the source/drain region. Claim 12 additionally recites the limitation, “the second side of the substrate,” in line 9 of the claim. There is insufficient antecedent basis for this limitation in the claim. For the purpose of this office action, this limitation is interpreted to have the following meaning: the back side of the substrate.
Claim 18 recites the limitation, “source/drain feature,” in lines 4, 6, 9-10 of the claim. The meets and bounds of the phrase, “source/drain feature,” are unclear, as it is unclear whether this phrase means a source/drain region itself or a separate feature, which is not the source/drain but instead is formed in proximity to the source/drain. The specification discloses features formed in a source/drain region (para. 27: el. 128) and discloses features formed adjacent to these epitaxial features 128 (para. 28, 34: el. 130, 132, 146), but does not provide clarity on the meaning of the phrase, “source/drain feature,” or clarity on which features or structures are associated with the meaning of the phrase. For the purpose of this office action, the limitation is interpreted to have the following meaning: the source/drain region.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2-3, 5-8, and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (US PGPub 20200126868 A1; hereinafter referred to as "Wang’868”).
Re claim 1: Wang’868 teaches a semiconductor device structure (title, abstract), comprising: a substrate having a front side and a back side opposing the front side (FIG. 18B: el. 50; para. 18); a gate stack disposed on the front side of the substrate (FIG. 18B: el. 106 and 108; para. 14); a first source/drain region (FIG. 18B: el. 92; para. 14) and a second source/drain region (FIG. 18B: el. 92; para. 14) disposed in opposing sides of the gate stack (annotated FIG. 18B: el. 92, (106, 108); para. 14 |1st and 2nd S/D regions 92 on opposing sides of gate stack (106 and 108) are labelled in annotated FIG. 18B, provided below), wherein each first source/drain region and second source/drain region comprises a first side and a second side (annotated FIG. 18B: el. 92 |1st and 2nd sides of 1st and 2nd S/D regions labelled in annotated FIG. 18B, provided below), and the second side of the first source/drain region and the back side of the substrate are at different elevations (annotated FIG. 18B: el. 2nd side of 1st S/D region, back side of substrate); and a conductive feature (FIG. 18B: el. 124; para. 64) in contact with the second side of the first source/drain region (annotated FIG. 18B: el. 124, 2nd side of 1st S/D region), wherein a portion of the back side of the substrate is exposed to air (annotated FIG. 18B: el. 50, back side of substrate| back side of substrate exposed to air at exterior surfaces of wafer).
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Re claim 2: Wang’868 teaches the semiconductor device structure of claim 1, further comprising: a contact etch stop layer (CESL) in contact with the first side of the first source/drain region (annotated FIG. 18B: el. 98, 1st side of 1st S/D region; para. 46| annotated FIG. 18B provided in Re claim 1 section).
Re claim 3: Wang’868 teaches the semiconductor device structure of claim 2, further comprising: a conductive feature in contact with the second side of the first source/drain region (annotated FIG. 18B: el. 124, 2nd side of 1st S/D region; para. 64| annotated FIG. 18B provided in Re claim 1 section).
Re claim 5: Wang’868 teaches the semiconductor device structure of claim 1, wherein a portion of the first source/drain region is exposed to the air (annotated FIG. 18B: el. 92 (1st S/D region), 94; para. 43, 70|1st S/D region 92 exposed to air by means of air in the void 94; annotated FIG. 18B provided in Re claim 1 section).
Re claim 6: Wang’868 teaches the semiconductor device structure of claim 5, wherein a portion of a sidewall of the first source/drain region is exposed to the air (annotated FIG. 18B: el. 92 (portion of sidewall of 1st S/D region), 94; para. 43, 70|portion of sidewall of 1st S/D region 92 exposed to air by means of air in the void 94; annotated FIG. 18B provided in Re claim 1 section).
Re claim 7: Wang’868 teaches the semiconductor device structure of claim 1, wherein the back side of the substrate and the second side of the second source/drain region are at different elevations (annotated FIG. 18B: el. back side of substrate, 2nd side of 2nd S/D region| annotated FIG. 18B provided in Re claim 1 section).
Re claim 8: Wang’868 teaches the semiconductor device structure of claim 7, further comprising: a dielectric layer (FIG. 18B: el. 114; para. 59) disposed to surround the sidewall of the conductive feature (FIG. 18B: el. 114, 124).
Re claim 12: Wang’868 teaches a semiconductor device structure, comprising: a substrate having a front side and a back side opposing the front side (FIG. 18B: el. 50; para. 18); a gate stack disposed at the front side of the substrate (FIG. 18B: el. 106 and 108; para. 14); a first source/drain region having a first side, and a second side opposing the first side (annotated FIG. 18B: el. 92| 1st and 2nd side of 1st S/D region labelled in annotated FIG. 18B, provided below), and a sidewall in contact with a first sidewall of the substrate (FIG. 17B: el. 92, 52; para. 13| FIG. 17B shows the cross-section which shows the S/D regions 92 having a sidewall in contact with a sidewall of the fin region 52 of the substrate); and a conductive feature in contact with the second side of the first source/drain region (annotated FIG. 18B: el. 124, 2nd side of 1st S/D region; para. 64| annotated FIG. 18B provided below), wherein the second side of the first source/drain region and the conductive feature define an interface that is at a different elevation with respect to the back side of the substrate (annotated FIG. 18B: el. 2nd side of first S/D feature, 124, back side of substrate| annotated FIG. 18B provided below), wherein the back side of the substrate, the sidewall of the first source/drain region are exposed to air (FIG. 17B: el. 50, 92, 94; para. 43, 70 |sidewall of 1st S/D region 92 exposed to air by means of air in the void 94, back side of substrate exposed air by means of air at exterior surfaces of wafer).
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Claims 1, 7-10, 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (US PGPub 20210083114 A1; hereinafter referred to as "Wang’114”).
Re claim 1 (mapped to Wang’114) : Wang’114 teaches a semiconductor device structure, comprising: a substrate having a front side and a back side opposing the front side (FIG. 8B: el. 202; para. 13); a gate stack disposed on the front side of the substrate (FIG. 8B: el. 210; para. 13); a first source/drain region and a second source/drain region disposed in opposing sides of the gate stack (FIG. 8B: el. 214; para. 13| 1st and 2nd S/D regions labelled in annotated FIG. 8B, provided below), wherein each first source/drain region and second source/drain region comprises a first side and a second side (annotated FIG. 8B: el. 214|1st and 2nd sides of 1st and 2nd S/D regions labelled in annotated FIG. 8B, provided below), and the second side of the first source/drain region and the back side of the substrate are at different elevations (annotated FIG. 8B: el. 2nd side of 1st S/D region, back side of substrate); and a conductive feature in contact with the second side of the first source/drain region (annotated FIG. 8B: el. (235, 236), 2nd side of 1st S/D region; para. 13), wherein a portion of the back side of the substrate is exposed to air.
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Re claim 7: Wang’114 teaches the semiconductor device structure of claim 1, wherein the back side of the substrate and the second side of the second source/drain region are at different elevations (annotated FIG. 8B: el. back side of substrate, 2nd side of 2nd S/D region| annotated FIG. 8B provided in Re claim 1 (mapped to Wang’114) section).
Re claim 8: Wang’114 teaches the semiconductor device structure of claim 7, further comprising: a dielectric layer disposed to surround the sidewall of the conductive feature (FIG. 8B: el. (220, 222), (235, 236); para. 13|dielectric layer formed of dielectric sub-layers 220 and 222 surround conductive feature formed of sub-layers 235 and 236).
Re claim 9: Wang’114 teaches the semiconductor device structure of claim 8, further comprising: a liner layer disposed between and in contact with the dielectric layer and the second side of the second source/drain region (annotated FIG. 8B: el. liner layer, (220, 222), 2nd side of 2nd S/D region| liner layer labelled in annotated FIG. 8B, provided in Re claim 1 (mapped to Wang’114) section).
Re claim 10: Wang’114 teaches the semiconductor device structure of claim 9, wherein the second side of the second source/drain region is exposed to the air (annotated FIG. 8B: el. 240b, 2nd side of 2nd S/D region; para. 29| 2nd side of 2nd S/D region exposed to air by contact with air gap 240b; annotated FIG. 8B provided in Re claim 1 (mapped to Wang’114) section).
Re claim 18: Wang-’114 teaches a semiconductor device structure, comprising: a substrate having a first side and a second side opposing the first side (FIG. 8B: el. 202; para. 13); a gate stack disposed at the first side of the substrate (FIG. 8B: el. 210; para. 13); a first source/drain region and a second source/drain region disposed in opposing regions of the gate stack (FIG. 8B: el. 214; para. 13); a conductive feature in contact with the first source/drain region (FIG. 8B: el. (235, 236), 214; para. 13|first source/drain region being considered as leftmost S/D feature of FIG. 8B); a dielectric layer enclosing the conductive feature (FIG. 8B: el. 220, 222; para. 13|dielectric layer formed of dielectric sub-layers 220 and 222); and a liner layer disposed between and in contact with the dielectric layer and the second source/drain region (annotated FIG. 8B|liner layer labelled in annotated FIG. 8B, provided below), wherein portions of the liner layer, the dielectric layer, the second source/drain region, the second side of the substrate, and the conductive feature are exposed to air (annotated FIG. 8B: el. liner layer, (220, 222), 2nd side of substrate, (235, 236)|para. 29|listed elements are exposed to air at exterior surfaces of wafer or by contact with air gap 240b; annotated FIG. 8B provided below).
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Re claim 19: Wang’114 teaches the semiconductor device structure of claim 18, wherein a portion of a sidewall of the first source/drain region is exposed to the air (annotated FIG. 8B: el. portion of sidewall of 1st S/D region exposed to air; para. 26| portion of sidewall of 1st S/D region exposed to air labelled in annotated FIG. 8B, provided in Re claim 18 section; silicide 234 is formed from diffusion between material of S/D region 214 and layer of metal formed above S/D region; as the silicide layer 234 is formed of material of the S/D region, the S/D region is considered to include silicide 234; portion of sidewall of 234 is exposed to air within air gap 240b).
Re claim 20: Wang’114 teaches the semiconductor device structure of claim 18, wherein the first source/drain region and the conductive feature define an interface, and the interface and the second side of the substrate are at different heights (annotated FIG. 8B: el. interface of conductive feature and 1st S/D region, 2nd side of substrate| interface labelled in annotated FIG. 8B, provided in Re claim 18 section).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Wang’868 in view of Block et al. (US PGPub 20200035560 A1; hereinafter referred to as "Block”) .
Re claim 11: Wang’868 is silent to the semiconductor device structure of claim 1, further comprising: a power rail in contact with the conductive feature.
In a similar field of endeavor, Block teaches a semiconductor device having source/drain regions on opposing sides of a gate (FIG. 12-13: el. 673), wherein a power rail is coupled to a conductive source/drain contact metallization which is coupled to the S/D region (para. 174). Block teaches semiconductor device comprising: a power rail in contact with the conductive S/D metallization feature. Block also teaches a benefit of coupling a power rail to the conductive feature is to render the device structure operable by providing power to the S/D region.
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Wang’868 and Block, to enable using the power rail of Block in the semiconductor device of Wang’868, for the benefit of rendering the device structure operable by providing power to the S/D region.
Allowable Subject Matter
Claims 4, 13-17 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Re claim 4: The closest prior art, Wang’868 (US PGPub 20200126868 A1), Wang’114 (US PGPub 20210083114 A1), and Block (US PGPub 20200035560 A1), either alone or in combination fails to disclose or suggest, “wherein a sidewall of the conductive feature is exposed to the air,” in combination with the additionally claimed features, as claimed by the applicant.
Re claim 13: The closest prior art, Wang’868 (US PGPub 20200126868 A1), Wang’114 (US PGPub 20210083114 A1), and Block (US PGPub 20200035560 A1), either alone or in combination fails to disclose or suggest, “wherein the conductive feature has a sidewall exposing to the air,” in combination with the additionally claimed features, as claimed by the applicant.
Re claim 14: The closest prior art, Wang’868 (US PGPub 20200126868 A1), Wang’114 (US PGPub 20210083114 A1), and Block (US PGPub 20200035560 A1), either alone or in combination fails to disclose or suggest, “wherein at least a portion of the dielectric layer is exposed to the air,” in combination with the additionally claimed features, as claimed by the applicant.
Re claim 15: The closest prior art, Wang’868 (US PGPub 20200126868 A1), Wang’114 (US PGPub 20210083114 A1), and Block (US PGPub 20200035560 A1), either alone or in combination fails to disclose or suggest, “wherein at least a portion of the dielectric layer is exposed to the air and wherein the dielectric layer is separated from the conductive feature by the air,” in combination with the additionally claimed features, as claimed by the applicant.
Re claim 16: The closest prior art, Wang’868 (US PGPub 20200126868 A1), Wang’114 (US PGPub 20210083114 A1), and Block (US PGPub 20200035560 A1), either alone or in combination fails to disclose or suggest, “wherein at least a portion of the dielectric layer is exposed to the air,” in combination with the additionally claimed features, as claimed by the applicant.
Re claim 17: The closest prior art, Wang’868 (US PGPub 20200126868 A1), Wang’114 (US PGPub 20210083114 A1), and Block (US PGPub 20200035560 A1), either alone or in combination fails to disclose or suggest, “wherein at least a portion of the dielectric layer is exposed to the air,” in combination with the additionally claimed features, as claimed by the applicant.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The prior art cited and not relied upon discloses a semiconductor devices with backside S/D contacts.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEVIN GOODLING whose telephone number is (571)272-2552. The examiner can normally be reached M-F 7:30am - 5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.G./Examiner, Art Unit 2898 /JULIO J MALDONADO/ Supervisory Patent Examiner, Art Unit 2898
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