Prosecution Insights
Last updated: October 01, 2026
Application No. 18/771,714

GATE STRUCTURES IN TRANSISTOR DEVICES AND METHODS OF FORMING SAME

Non-Final OA §DP
Filed
Jul 12, 2024
Priority
Jul 08, 2021 — provisional 63/219,416 +1 more
Examiner
BOWEN, ADAM S
Art Unit
Tech Center
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
96%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 96% — above average
96%
Career Allowance Rate
718 granted / 744 resolved
+36.5% vs TC avg
Minimal +2% lift
Without
With
+2.4%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 9m
Avg Prosecution
25 currently pending
Career history
748
Total Applications
across all art units

Statute-Specific Performance

§101
2.4%
-37.6% vs TC avg
§103
46.0%
+6.0% vs TC avg
§102
33.5%
-6.5% vs TC avg
§112
5.6%
-34.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 744 resolved cases

Office Action

§DP
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statements (IDS) submitted on 07/12/2024, 08/14/2024 and 02/10/2026 were filed before the first action on the merits. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,087,775. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 1 of U.S. Patent No. 12,087,775 recites all of the limitations in claim 1 of the instant application. Claim 2 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,087,775. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 1 of U.S. Patent No. 12,087,775 recites all of the limitations in claim 2 of the instant application. Claim 3 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 2 of U.S. Patent No. 12,087,775. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 2 of U.S. Patent No. 12,087,775 recites all of the limitations in claim 3 of the instant application. Claim 4 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 4 of U.S. Patent No. 12,087,775. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 4 of U.S. Patent No. 12,087,775 recites all of the limitations in claim 4 of the instant application. Claim 5 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 5 of U.S. Patent No. 12,087,775. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 5 of U.S. Patent No. 12,087,775 recites all of the limitations in claim 5 of the instant application. Claim 8 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 7 of U.S. Patent No. 12,087,775. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 7 of U.S. Patent No. 12,087,775 recites all of the limitations in claim 8 of the instant application. Claim 9 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 8 of U.S. Patent No. 12,087,775. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 8 of U.S. Patent No. 12,087,775 recites all of the limitations in claim 9 of the instant application. Claim 10 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 9 of U.S. Patent No. 12,087,775. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 9 of U.S. Patent No. 12,087,775 recites all of the limitations in claim 10 of the instant application. Claim 11 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 10 of U.S. Patent No. 12,087,775. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 10 of U.S. Patent No. 12,087,775 recites all of the limitations in claim 11 of the instant application. Claim 13 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 10 of U.S. Patent No. 12,087,775. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 10 of U.S. Patent No. 12,087,775 recites all of the limitations in claim 13 of the instant application. Claim 14 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 7 of U.S. Patent No. 12,087,775. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 7 of U.S. Patent No. 12,087,775 recites all of the limitations in claim 14 of the instant application. Claim 15 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 14 of U.S. Patent No. 12,087,775. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 14 of U.S. Patent No. 12,087,775 recites all of the limitations in claim 15 of the instant application. Claim 16 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 14 of U.S. Patent No. 12,087,775. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 14 of U.S. Patent No. 12,087,775 recites all of the limitations in claim 16 of the instant application. Claim 17 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 15 of U.S. Patent No. 12,087,775. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 15 of U.S. Patent No. 12,087,775 recites all of the limitations in claim 17 of the instant application. Claim 18 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 17 of U.S. Patent No. 12,087,775. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 17 of U.S. Patent No. 12,087,775 recites all of the limitations in claim 18 of the instant application. Claim 20 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 19 of U.S. Patent No. 12,087,775. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 19 of U.S. Patent No. 12,087,775 recites all of the limitations in claim 20 of the instant application. Prior art of record Re claim 1, Park et al. (2022/0013630) teaches a semiconductor device (Fig. 11) comprising: a first fin (AP1) and a second fin (AP2); a first gate stack (GS1) over the first fin (AP1); a second gate stack (GS2) over the second fin (AP2); and a gate isolation structure (DB1) separating the first gate stack (GS1) from the second gate stack (GS2), and wherein the gate isolation structure (DB1) comprises: a dielectric liner (176) along sidewalls of the gate isolation structure (DB1); and a dielectric fill material (170) surrounded by the dielectric liner (176). Park does not explicitly teach wherein the dielectric liner has a tapered profile with a first thickness at a top of the gate isolation structure and a second thickness at a bottom of the first gate stack, wherein the first thickness is less than the second thickness, wherein the dielectric liner extends continuously from a sidewall of the first gate stack to a sidewall of the second gate stack. Re claim 8, Park et al. (2022/0013630) teaches a semiconductor device (Fig. 11) comprising: a first gate stack (GS1) and a second gate stack (GS2); and a gate isolation structure (DB1) contacting a sidewall of the first gate stack (GS1) and a sidewall of the second gate stack (GS2), wherein the gate isolation structure (DB1) comprises: a dielectric liner (176); and a dielectric fill material (170) over the dielectric liner (176), wherein the dielectric liner (176) separates the dielectric fill material (170) from the first gate stack (GS1) and the second gate stack (GS2). Park does not explicitly teach wherein a first lateral dimension of the dielectric liner is less than a second lateral dimension of the dielectric liner, wherein the first lateral dimension of the dielectric liner is measured at a level of a top surface of the first gate stack, wherein the second lateral dimension of the dielectric liner is measured at a level of a bottom surface of the first gate stack. Re claim 15, Kwak et al. (2018/0090493) teaches a method (Figs. 1-36) comprising: patterning an opening (160t) extending through a dummy gate stack (Figs. 25-29); depositing a dielectric liner (161t) on sidewalls and a bottom surface of the opening (Fig. 30), wherein depositing the dielectric liner comprises forming the dielectric liner to have a varied width [72, 172]; depositing a dielectric fill material (162p, [172]) in the opening over the dielectric liner (161t), wherein depositing the dielectric fill material comprises a different type of deposition process than depositing the dielectric liner [73, 90]. Kwak does not explicitly teach removing the dummy gate stack to define a first gate opening and a second gate opening; and forming a first gate stack in the first gate opening and a second gate stack in the second gate opening such that the first gate stack and the second gate stack each physically contact the dielectric liner. Allowable Subject Matter The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not anticipate or make obvious the device of claim 1, including each of the limitations and specifically wherein the dielectric liner has a tapered profile with a first thickness at a top of the gate isolation structure and a second thickness at a bottom of the first gate stack, wherein the first thickness is less than the second thickness, wherein the dielectric liner extends continuously from a sidewall of the first gate stack to a sidewall of the second gate stack, for the same reasons as mentioned for claim 1 in the prior art of record above. The prior art of record does not anticipate or make obvious the device of claim 8, including each of the limitations and specifically wherein a first lateral dimension of the dielectric liner is less than a second lateral dimension of the dielectric liner, wherein the first lateral dimension of the dielectric liner is measured at a level of a top surface of the first gate stack, wherein the second lateral dimension of the dielectric liner is measured at a level of a bottom surface of the first gate stack, for the same reasons as mentioned for claim 8 in the prior art of record above. The prior art of record does not anticipate or make obvious the method of claim 15, including each of the limitations and specifically removing the dummy gate stack to define a first gate opening and a second gate opening; and forming a first gate stack in the first gate opening and a second gate stack in the second gate opening such that the first gate stack and the second gate stack each physically contact the dielectric liner, for the same reasons as mentioned for claim 15 in the prior art of record above. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM S BOWEN whose telephone number is (571)272-3984. The examiner can normally be reached M-F 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ADAM S BOWEN/Examiner, Art Unit 2897 /FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
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Prosecution Timeline

Jul 12, 2024
Application Filed
Sep 15, 2026
Non-Final Rejection mailed — §DP (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
96%
Grant Probability
99%
With Interview (+2.4%)
1y 9m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 744 resolved cases by this examiner. Grant probability derived from career allowance rate.

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