Prosecution Insights
Last updated: April 19, 2026
Application No. 18/771,753

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Non-Final OA §112§DP
Filed
Jul 12, 2024
Examiner
NGUYEN, CUONG B
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company Ltd.
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
2y 5m
To Grant
99%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allow Rate
824 granted / 938 resolved
+19.8% vs TC avg
Strong +16% interview lift
Without
With
+16.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
48 currently pending
Career history
986
Total Applications
across all art units

Statute-Specific Performance

§101
0.9%
-39.1% vs TC avg
§103
41.9%
+1.9% vs TC avg
§102
33.8%
-6.2% vs TC avg
§112
18.6%
-21.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 938 resolved cases

Office Action

§112 §DP
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Response to Amendment Applicant's amendment to the claims, filed on September 12th, 2025, is acknowledged. Entry of amendment is accepted and made of record. Election/Restrictions Applicant's election without traverse of Species I directed to Figs. 1-15 (claims 1-20) in the reply filed on September 12th, 2025 is acknowledged. Claim Objections Claims 1, 6 and 15 are objected to because of the following informalities: Claim 1 recites “the fin structures” in lines 5 and 6 refers back to “a plurality of fin structure” in line 2 and should be amended to “the plurality of fin structure” for avoiding confusing. Appropriate correction is required. Claim 1 recites “the second portions of the fin structures of adjacent fin structures” in lines 18-19 should be amended to “the second portions of adjacent fins structures of the plurality of fin structures” for being consistent with the language in line 2. Appropriate correction is required. Claim 1 recites “the third concentration” in line 12 should be amended to “the third concentration of the dopant” for being consistent with the language in lines 10-11. Appropriate correction is required. Claim 1 recites “the second concentration” in line 12 should be amended to “the second concentration of the dopant” for being consistent with the language in line 11. Appropriate correction is required. Claim 1 recites “the first concentration” in line 13 should be amended to “the first concentration of the dopant” for being consistent with the language in lines 8-9. Appropriate correction is required. Claim 6 recites “the fin structures” in lines 4 and 5 refers back to “a plurality of fin structure” in line 2 and should be amended to “the plurality of fin structure” for avoiding confusing. Appropriate correction is required. Claim 15 recites “adjacent fin structures” in lines 14-15 should be amended to “adjacent fins structures of the plurality of fin structures” for being consistent with the language in line 2. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claims 6-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Claim 6 recites “the depth of the second epitaxial layers” in line 14-15. There is insufficient antecedent basis for this limitation in the claim. Furthermore, claim 6 recites “a height of the depth of the second epitaxial layers” in line 14-15. Is it unclear to the examiner if the limitation is reciting a height or a depth for the second epitaxial layers. Claims 7-14 are rejected for being depended on claim 6 because of the above issues incorporating into the claims. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp. Claims 1-12 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-5 and 14-20 of U.S. Patent No. 12,087,846. Although the claims at issue are not identical, they are not patentably distinct from each other because the language of the claims have the same meaning. Instant Application: U.S. Patent No. 12,087,846: Claim 1. A semiconductor device, comprising: a plurality of fin structures extending in a first direction over a substrate; a gate structure extending in a second direction crossing the first direction disposed over a first portion of the fin structures; and epitaxial source/drain structures disposed over second portions of the fin structures, wherein the second portions of the fin structures are located on opposing sides of the gate structure; wherein the epitaxial source/drain structures include a first layer having a first concentration of a dopant, a second layer having a second concentration of the dopant, the second layer is disposed over the first layer, a third layer having a third concentration of the dopant, and the third layer is disposed over the second layer, wherein the third concentration is greater than the second concentration, and the second concentration is greater than the first concentration, wherein each of the epitaxial source/drain structures is a merged source/drain structure, wherein at least the third layers of adjacent epitaxial source/drain structures are merged, and wherein a height in a third direction substantially perpendicular to the first and second directions from a level of upper surfaces of the second portions of the fin structures of adjacent fin structures to an uppermost point of a lower surface of the merged adjacent epitaxial source/drain structures is greater than a thickness of the merged source/drain structure in the third direction from the uppermost point of the lower surface of the merged adjacent epitaxial source/drain structures to a top surface of the merged adjacent epitaxial source/drain structures. Claim 1. A semiconductor device, comprising: a plurality of fin structures extending in a first direction over a substrate; a gate structure extending in a second direction crossing the first direction disposed over a first portion of the plurality of fin structures; a fin mask layer disposed on sidewalls of the plurality of fin structures; and epitaxial source/drain structures disposed over second portions of the plurality of fin structures, wherein the second portions of the fin structures are located on opposing sides of the gate structure; wherein the epitaxial source/drain structures include a first layer having a first concentration of a dopant, a second layer having a second concentration of the dopant, the second layer is disposed over the first layer, a third layer having a third concentration of the dopant, and the third layer is disposed over the second layer, wherein the third concentration of the dopant is greater than the second concentration of the dopant, and the second concentration of the dopant is greater than the first concentration of the dopant, wherein each of the epitaxial source/drain structures is a merged source/drain structure, wherein at least the third layers of adjacent epitaxial source/drain structures are merged, and wherein a height in a third direction substantially perpendicular to the first and second directions from a level of upper surfaces of the second portions of the fin structures of adjacent fin structures to an uppermost point of a lower surface of the merged adjacent epitaxial source/drain structures is greater than a thickness of the merged source/drain structure in the third direction from the uppermost point of the lower surface of the merged adjacent epitaxial source/drain structures to a top surface of the merged adjacent epitaxial source/drain structures. Claim 2. The semiconductor device of claim 1, wherein the third concentration of the dopant ranges from 1 x 1021 atoms/cm3 to 5 x 1021 atoms/cm3. Claim 2. The semiconductor device of claim 1, wherein the third concentration of the dopant ranges from 1 x 1021 atoms/cm3 to 5 x 1021 atoms/cm3. Claim 3. The semiconductor device of claim 1, wherein the third concentration of the dopant ranges from 3 x 1021 atoms/cm3 to 4.5 x 1021 atoms/cm3. Claim 3. The semiconductor device of claim 1, wherein the third concentration of the dopant ranges from 3 x 1021 atoms/cm3 to 4.5 x 1021 atoms/cm3. Claim 4. The semiconductor device of claim 1, wherein the second concentration of the dopant ranges from 9.0 x 1020 atoms/cm3 to 2 x 1021 atoms/cm3. Claim 4. The semiconductor device of claim 1, wherein the second concentration of the dopant ranges from 9.0 x 1020 atoms/cm3 to 2 x 1021 atoms/cm3. Claim 5. The semiconductor device of claim 1, wherein a ratio of the height in the third direction to the thickness of the merged adjacent epitaxial source/drain structures ranges from 1.05 to 3.0. Claim 5. The semiconductor device of claim 1, wherein a ratio of the height in the third direction to the thickness of the merged adjacent epitaxial source/drain structures ranges from 1.05 to 3.0. Claim 6. A semiconductor device, comprising: a plurality of fin structures extending in a first direction disposed over a substrate; a gate structure extending in a second direction crossing the first direction disposed over a first portion of the fin structures; first epitaxial layers disposed over second portions of each of the fin structures, wherein the second portions are located on opposing sides of the gate structure, and an uppermost surface of the second portions is at a level below uppermost surfaces of the first portions as viewed in cross section; second epitaxial layers disposed over the first epitaxial layers, wherein the first and second epitaxial layers are U-shaped as viewed in cross section; third epitaxial layers disposed over the second epitaxial layers and filling the U-shape of the first and second epitaxial layers, wherein the third epitaxial layers extend into the second epitaxial layers to a depth from an uppermost surface of the second epitaxial layers greater than half a height of the depth of the second epitaxial layers as viewed in cross section, wherein the height of the second epitaxial layer is measured from a lowermost surface of the second epitaxial layer to the uppermost surface of the second epitaxial layer, wherein a concentration of dopant in the third epitaxial layers is greater than a concentration of the dopant in the second epitaxial layers, and the concentration of the dopant in the second epitaxial layers is greater than a concentration of the dopant in the first epitaxial layers; and fourth epitaxial layers having a concentration of a dopant less than the concentration of the dopant in the third epitaxial layers disposed over the third epitaxial layers, wherein the dopant in the fourth epitaxial layers is same as or different than the dopant in the third epitaxial layers. Claim 14. A semiconductor device, comprising: a plurality of fin structures extending in a first direction disposed over a substrate; a gate structure extending in a second direction crossing the first direction disposed over a first portion of the plurality of fin structures; a fin mask layer disposed on sidewalls of the plurality of fin structures; first epitaxial layers disposed over second portions of each of the plurality of fin structures, wherein the second portions are located on opposing sides of the gate structure, and an uppermost surface of the second portions is at a level below uppermost surfaces of the first portions as viewed in cross section; second epitaxial layers disposed over the first epitaxial layers, wherein the first and second epitaxial layers are U-shaped as viewed in cross section; third epitaxial layers disposed over the second epitaxial layers and filling the U-shape of the first and second epitaxial layers, wherein the third epitaxial layers extend into the second epitaxial layers to a depth from an uppermost surface of the second epitaxial layers greater than half a height of the second epitaxial layers as viewed in cross section, wherein the height of the second epitaxial layers is measured from a lowermost surface of the second epitaxial layer to the uppermost surface of the second epitaxial layer, wherein a concentration of dopant in the third epitaxial layers is greater than a concentration of the dopant in the second epitaxial layers, and the concentration of the dopant in the second epitaxial layers is greater than a concentration of the dopant in the first epitaxial layers; and fourth epitaxial layers having a concentration of a dopant less than the concentration of the dopant in the third epitaxial layers disposed over the third epitaxial layers, wherein the dopant in the fourth epitaxial layers is same as or different than the dopant in the third epitaxial layers. Claim 7. The semiconductor device of claim 6, wherein the third concentration of the dopant ranges from 1 x 1021 atoms/cm3 to 5 x 1021 atoms/cm3. Claim 15. The semiconductor device of claim 14, wherein the third concentration of the dopant ranges from 1 x 1021 atoms/cm3 to 5 x 1021 atoms/cm3. Claim 8. The semiconductor device of claim 6, wherein the second concentration of the dopant ranges from 9.0 x 1020 atoms/cm3 to 2 x 1021 atoms/cm3. Claim 16. The semiconductor device of claim 14, wherein the second concentration of the dopant ranges from 9.0 x 1020 atoms/cm3 to 2 x 1021 atoms/cm3. Claim 9. The semiconductor device of claim 6, wherein the fourth epitaxial layers comprise silicon and germanium. Claim 17. The semiconductor device of claim 14, wherein the fourth epitaxial layers comprise silicon and germanium. Claim 10. The semiconductor device of claim 6, further comprising a metal-semiconductor compound layer disposed over the fourth epitaxial layers. Claim 18. The semiconductor device of claim 14, further comprising a metal-semiconductor compound layer disposed over the fourth epitaxial layers. Claim 11. The semiconductor device of claim 6, wherein at least the third epitaxial layers disposed over adjacent fin structures are merged. Claim 19. The semiconductor device of claim 14, wherein at least the third epitaxial layers disposed over adjacent fin structures are merged. Claim 12. The semiconductor device of claim 11, wherein a thickness of the merged third epitaxial layers ranges from 20 nm to 25 nm. Claim 20. The semiconductor device of claim 14, wherein a thickness of the merged third epitaxial layers ranges from 20 nm to 25 nm. Allowable Subject Matter Claims 13-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is an examiner's statement of reasons for the indication of allowable subject matter: The cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to disclose or suggest the claimed invention having: wherein the dopant is at least one selected from the group consisting of As, P, and Sb as recited in claim 13; and The semiconductor device of claim 6, wherein the third epitaxial layers comprise SiP as recited in claim 14. Claims 15-20 would be allowed over prior art of record if amended to overcome the objection as set forth in the office action. The following is an examiner’s statement of reason for allowance: the prior art of record does not teach or suggest the limitation as following: Regarding claim 15, KIM et al. (Pub. No.: US 2017/0148797 A1) discloses a semiconductor device, comprising: a plurality of fin structures (102/104) extending in a first direction over a substrate (100) (see Fig. 10 and [0109-0110]); a gate structure (282/284) extending in a second direction crossing the first direction disposed over a first portion of the fin structures (see Fig. 32-34 and [0168]); a fin mask layer (120) disposed on sidewalls of the fin structure and epitaxial source/drain structures (204a/204b/204c) disposed over second portions of the fin structures (see Fig. 29 and [0113]), wherein the second portions of the fin structures are located on opposing sides of the gate structure (see Fig. 35 and [0131-0133], [0144]); wherein the epitaxial source/drain structures include a first layer (204a) having a first concentration of a dopant, a second layer (204b) having a second concentration of the dopant, the second layer is disposed over the first layer, a third layer (204c) having a third concentration of the dopant, and the third layer is disposed over the second layer, wherein the third concentration is greater than the second concentration, and the second concentration is greater than the first concentration, wherein each of the epitaxial source/drain structures is a merged source/drain structure (see Fig. 29), wherein at least the third layers (204c) of adjacent epitaxial source/drain structures are merged (see Fig. 29 and [0161-0167]); and cap layers (capping layers 214) having a fourth concentration of the dopant disposed over the epitaxial source/drain structures (see [0149]). KIM et al. fails to disclose wherein a height in a third direction substantially perpendicular to the first and second directions from a level of upper surfaces of the second portions of the fin structures of adjacent fin structures to an uppermost point of a lower surface of the merged adjacent epitaxial source/drain structures is greater than a thickness of the merged source/drain structure in the third direction from the uppermost point of the lower surface of the merged adjacent epitaxial source/drain structures to a top surface of the merged adjacent epitaxial source/drain structures and wherein the fourth concentration of the dopant is less than the third concentration of the dopant as recited in claim 15. Claims 14-20 depend on claim 15, and therefore also include said claimed limitation. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CUONG B NGUYEN/Primary Examiner, Art Unit 2818
Read full office action

Prosecution Timeline

Jul 12, 2024
Application Filed
Nov 13, 2025
Non-Final Rejection — §112, §DP (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
99%
With Interview (+16.0%)
2y 5m
Median Time to Grant
Low
PTA Risk
Based on 938 resolved cases by this examiner. Grant probability derived from career allow rate.

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