DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 6, 11-13, and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chuang et al. (US 2014/0353819, hereinafter, Chuang.)
In regard to claims 1, 11, and 17, in figs. 5-9, Chuang discloses, a semiconductor structure 100, comprising:
an interconnect structure comprising conductive features 30;
a dielectric layer 42 over the interconnect structure;
an insulation structure 58 over the dielectric layer;
a first redistribution feature 62A or 62B including a first line portion disposed over the
insulation structure and a first via portion extending through the insulation structure;
a second redistribution feature 62c including a second line portion disposed over the
insulation structure and a second via portion extending through the insulation structure; and
a dummy metal feature 48 disposed in the dielectric layer and insulated from all of
the conductive features in the interconnect structure, wherein the first line portion is spaced apart from the second line portion along a first direction by a spacing, wherein a vertical projection of the spacing overlaps a portion of the dummy metal feature.
Furthermore, regarding claim 17, the structure further includes a plurality of transistors, 12, for example;
an interconnect structure electrically coupled to the plurality of transistors;
the metal feature disposed over the interconnect structure and electrically isolated
from the plurality of transistors (para [0010] and fig. 1.)
Regarding claim 2, wherein the dummy metal feature comprises copper (Cu), (para [0018].)
Regarding claim 6, wherein the dummy metal feature does not simultaneously contact the first via portion and the second via portion. Fig. 9.
Regarding claim 12, wherein each of the plurality of dummy metal fragments comprises a width along the direction,
wherein the plurality of dummy metal fragments are disposed at a pitch along the
direction. Fig. 9.
Regarding claim 13, wherein the first line portion is spaced apart from the second line portion along a first direction by a spacing,
wherein the width is between about 10% and about 35 percent of the spacing. Fig. 9.
Regarding claim 18, wherein the metal feature, the first redistribution feature and the second redistribution feature extend lengthwise along a direction. Fig. 9.
Allowable Subject Matter
Claims 3-5, 7-10, 14-16, and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art does not show the insulation structure comprises:
a first insulation layer;
a passive device disposed over the first insulation layer; and
a second insulation layer over the passive device.
And a first etch stop layer (ESL) between the dielectric layer and the insulation
structure; and
a second ESL between the first ESL and the insulation structure.
And a passivation layer extending conformally along surfaces of the first line portion,
a top surface of the insulation structure, surfaces of the second line portion; and
a polymer layer disposed over the passivation layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN W HA whose telephone number is (571)272-1707. The examiner can normally be reached M-T: 8:00AM-6:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WAEL FAHMY can be reached at (571)-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NATHAN W HA/Primary Examiner, Art Unit 2814
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