DETAILED ACTION
The action is responsive to the following communications: the Application filed July 12, 2024 and the information disclosure statement (IDS) filed July 12, 2024. This application is a CON of 18/295,134.
Claims 1-20 are pending. Claims 1, 13 and 17 are independent.
Notice of Pre-AIA or AIA Status
The present application is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on July 12, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Independent claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over independent claims 1-20 of US Patent No. 12,080,704. Although the claims at issue are not identical, they are not patentably distinct from each other.
Instant Application
US Patent 12,080,704
Comment
Claim 1. A memory circuit comprising: a first bit line;
a second bit line;
a first memory cell including a first storage node and a second storage node, the first storage node being coupled to the second bit line, and the second storage node is not coupled to any bit line;
a first P-type pass gate transistor coupled between the first storage node and the second bit line;
a pre-charge circuit coupled to at least the first bit line or the second bit line, the pre-charge circuit configured to charge at least the first bit line or the second bit line to a pre-charge voltage responsive to a first signal, the pre-charge voltage being between a voltage of a first logical level and a voltage of a second logical level;
a first transmission gate coupled to the second bit line, and configured to receive a first control signal and a second control signal inverted from the first control signal; and
a sense amplifier coupled to the second bit line by the first transmission gate.
Claim 1. A memory circuit comprising:
a first bit line;
a second bit line;
a first inverter coupled to a first storage node and a second storage node;
a second inverter coupled to the first storage node, the second storage node and the first inverter, the second storage node is not coupled to any bit line;
a P-type pass gate transistor coupled between the first storage node and the first bit line;
a pre-charge circuit coupled to at least the first bit line or the second bit line, the pre-charge circuit configured to charge at least the first bit line or the second bit line to a pre-charge voltage responsive to a first signal, the pre-charge voltage being between a voltage of a first logical level and a voltage of a second logical level;
a first transmission gate coupled to the first bit line, and configured to receive a first control signal and a second control signal inverted from the first control signal; and
a sense amplifier coupled to the first bit line by the first transmission gate.
Note footnote1
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Houston et al. (US 2010/0296334) in view of Su (US 5,943,278).
Regarding independent claims 1 and 13, and its method independent claim 17, Houston et al. teach a memory circuit (see FIG. 3) comprising:
a first bit line (3046);
a second bit line (3024);
a first memory cell (3002) including a first storage node (3010) and a second storage node (3016), the first storage node (3010) being coupled to the second bit line (3024), and the second storage node (3016) is not coupled to any bit line (3016 not coupled to any bit line);
a first P-type pass gate transistor (3022) coupled between the first storage node (3010) and the second bit line (3024).
Houston et al. do not explicitly disclose a pre-charge circuit, a transmission gate and sense amplifier as claimed.
Su teaches the deficiencies in e.g., FIG. 4 along with prior art of Su, i.e.,
a pre-charge circuit (FIG. 2: M10) coupled to at least the first bit line or the second bit line, the pre-charge circuit configured to charge at least the first bit line or the second bit line to a pre-charge voltage responsive to a first signal, the pre-charge voltage being between a voltage of a first logical level and a voltage of a second logical level (Vcc-Vt);
a first transmission gate (FIG. 4: M3-4) coupled to the second bit line (BL, i.e., Houston’s active data line), and configured to receive a first control signal (Y0) and a second control signal (Y0B) inverted (i.e., “B) from the first control signal; and
a sense amplifier (SA) coupled to the second bit line (BL) by the first transmission gate (M3-4).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Su to the teaching of Houston et al. such that a memory, as taught by Houston et al., utilizes data read path, as taught by Su, for the purpose of performing memory read operations effectively, further claimed data read path is a well-known technology in a memory device because these conventional technology are well established in the art of the memory devices.
Further, regarding method claim 17, MPEP 2112.02(I) instructs examiners, “Under the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device will inherently perform the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed. Cir. 1986).” Here, the applied prior art product is identical to applicant’s disclosed product, and therefore is assumed, in accordance with MPEP 2112.02(I), to inherently perform the claimed process.
Regarding claims 2 and 14, Houston et al. and Su, as combined, teach the limitations of claims 1 and 13, respectively.
Su further teaches an equalization circuit (FIG. 4, top transistor) coupled between the first bit line and the second bit line, the equalization circuit configured to equalize a voltage of the first bit line and a voltage of the second bit line to the pre-charge voltage responsive to a second signal.
It would have been obvious to one of ordinary skill in the art before the effective filing date to further modify the invention of Su for the same purpose of performing memory read operations effectively, further claimed an equalization circuit is a well-known technology in a memory device because these conventional technology are well established in the art of the memory devices.
Regarding claims 3-4, Houston et al. and Su, as combined, teach the limitations of claim 2.
Houston and Su do not explicitly disclose the equalization circuit comprises: a first transistor of a first type comprising: a gate terminal of the first transistor being configured to receive the second signal; a drain terminal of the first transistor being coupled to the first bit line; and a source terminal of the first transistor being coupled to the second bit line; and the first type is a p-type.
However, claimed an equalization circuit is a well-known technology in a memory device.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize static random access memory used equalization circuits because these conventional technology are well established in the art of the memory devices.
Regarding claim 5, Houston et al. and Su, as combined, teach the limitations of claim 1.
Su further teaches the pre-charge circuit includes a first N-type transistor (FIG. 2: M10) having a first threshold value (Vcc-Vt).
It would have been obvious to one of ordinary skill in the art before the effective filing date to further modify the invention of Su for the same purpose of performing memory read operations effectively.
Regarding claims 6 and 16, Houston et al. and Su, as combined, teach the limitations of claims 1 and 15, respectively.
Su further teaches a first write driver coupled to the first bit line and the second bit line, the first write driver comprising: an input terminal configured to receive a data signal; and an output terminal coupled to the first bit line at a first node, and coupled to the second bit line at a second node (see FIG. 4; further claimed a write driver circuit is a well-known technology in a memory device).
It would have been obvious to one of ordinary skill in the art before the effective filing date to further modify the invention of Su for the same purpose of performing memory read/write operations effectively, further claimed a write driver circuit is a well-known technology in a memory device because these conventional technology are well established in the art of the memory devices.
Regarding claims 7-8 and 15, Houston et al. and Su, as combined, teach the limitations of claims 6 and 13, respectively.
Su further teaches a second transmission gate coupled to the first bit line at the first node, and further coupled to the first transmission gate, and configured to receive the first control signal and the second control signal; and sense amplifier is further coupled to the second transmission gate, and further coupled to the first bit line by the second transmission gate (see e.g., FIG. 4; further claimed data read path circuit is a well-known technology in a memory device).
Regarding claim 9, Houston et al. and Su, as combined, teach the limitations of claim 1.
Houston et al. further teach a second memory cell including a third storage node and a fourth storage node, the third storage node being coupled to the first bit line, and the fourth storage node is not coupled to any bit line; and a second P-type pass gate transistor coupled between the third storage node and the first bit line (see FIG. 3).
Regarding claim 10, Houston et al. and Su, as combined, teach the limitations of claim 1.
Houston et al. Su do not explicitly disclose the first memory cell is a five transistor (5T) static random access memory (SRAM) memory cell.
However, 5T P-type pass transistor SRAM cell is well-known technology for a type of memory for its purpose.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize static random access memory used 5T SRAM because these conventional technology are well established in the art of the memory devices.
Regarding claim 11, Houston et al. and Su, as combined, teach the limitations of claim 1.
Su further teaches the pre-charge circuit comprises: a first N-type transistor comprising: a gate terminal of the first N-type transistor (FIG. 2: M10) being configured to receive the first signal; a source terminal of the first N-type transistor being coupled to the first bit line; and a drain terminal of the first N-type transistor being coupled to at least a first supply voltage (FIG. 2).
Regarding claim 12, Houston et al. and Su, as combined, teach the limitations of claim 11.
Su’s pre-charge circuit do not explicitly disclose a second N-type transistor comprising: a gate terminal of the second N-type transistor being configured to receive the first signal; a source terminal of the second N-type transistor being coupled to the second bit line; and a drain terminal of the second N-type transistor being coupled to at least the first supply voltage.
However N-type transistor pre-charge circuit is a well-known technology for a type of memory for its purpose.
For support, of the above asserted facts, see for example, Schneider (US 6,108,256), FIG. 1 and accompanying disclosure.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize static random access memory used N-type pre-charge circuits because these conventional technology are well established in the art of the memory devices.
Regarding claims 18-20, Houston et al. and Su, as combined, teach the limitations of claim 17.
Su further teaches the pre-charging the first bit line and the second bit line comprises: turning on a first transistor of a first type responsive to the first signal thereby pulling a voltage of the first bit line towards the pre-charge voltage, the first transistor of the first type being the first N-type transistor; the pre-charging the first bit line and the second bit line further comprises: turning on a second transistor of the first type responsive to the first signal thereby pulling a voltage of the second bit line towards the pre-charge voltage; and turning on the sense amplifier responsive to a third signal, the third signal being different from the first signal and the second signal (e.g., FIG. 4 along with pre-charging circuitry shown in FIG. 2, and accompanying disclosure).
Further, regarding method claims, MPEP 2112.02(I) instructs examiners, “Under the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device will inherently perform the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed. Cir. 1986).” Here, the applied prior art product is identical to applicant’s disclosed product, and therefore is assumed, in accordance with MPEP 2112.02(I), to inherently perform the claimed process.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached on M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
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/SUNG IL CHO/Primary Examiner, Art Unit 2825
1 Re independent claims 1, 13 and 17, claims of US Patent recites all the claimed limitations. The various dependent claims are anticipated by/obvious in view of the conflicting patent.