DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/13/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-3 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3 of U.S. Patent No. 12,074,111. Although the claims at issue are not identical, they are not patentably distinct from each other because the conflicting claims have been patented.
Regarding claim 1, Pat '111 discloses, in claim 1, a semiconductor device structure, comprising:
a gate dielectric layer; a gate electrode layer in contact with the gate dielectric layer; an isolation layer disposed over the gate electrode layer; a first sidewall spacer in contact with the gate dielectric layer (all limitations are the same with the limitations recited in claim 1 of Pat '111); and
a liner layer having a first portion disposed between the isolation layer and the gate electrode layer and a second portion in contact with the first sidewall spacer ("a liner layer having a first portion disposed between the isolation layer and the gate electrode layer and a second portion disposed between and in contact with the first sidewall spacer and the SAC layer", in claim 1 of Pat '111, is interpreted as the same limitation). as described above.
Regarding claim 2, Pat '111 discloses the semiconductor device structure of claim 1 as described above.
Pat '111 further discloses, in claim 2, the liner layer is further in contact with the gate dielectric layer (all limitations are the same with the limitations recited in claim 2 of Pat '111).
Regarding claim 3, Pat '111 discloses the semiconductor device structure of claim 1 as described above.
Pat '111 further discloses, in claim 3, the liner layer is a dielectric layer that is free of oxygen atoms (all limitations are the same with the limitations recited in claim 3 of Pat '111).
Claims 11-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2, 4-7 and 9-10 of U.S. Patent No. 11,640,941. Although the claims at issue are not identical, they are not patentably distinct from each other because the conflicting claims have been patented.
Regarding claim 11, Pat '941 discloses, in claim 1, a semiconductor device structure, comprising:
a gate dielectric layer; a gate electrode layer in contact with the gate dielectric layer; an isolation layer disposed over the gate electrode layer; a metal layer disposed between and in contact with the gate electrode layer and the isolation layer (all limitations are the same with the limitations recited in claim 1 of Pat '941); and
a first sidewall spacer in contact with the gate dielectric layer and the isolation layer ("a first sidewall spacer in contact with the gate dielectric layer, the isolation layer, and the first SAC layer", in claim 1 of Pat '941, is interpreted as the same limitation).
Regarding claim 12, Pat '941discloses the semiconductor device structure of claim 11 as described above.
Pat '941 further discloses, in claim 2, the isolation layer is formed of a dielectric material free of oxygen atoms (all limitations are the same with the limitations recited in claim 2 of Pat '941).
Regarding claim 13, Pat '941discloses the semiconductor device structure of claim 11 as described above.
Pat '941 further discloses, in claim 4, the metal layer is further in contact with the gate dielectric layer (all limitations are the same with the limitations recited in claim 4 of Pat '941).
Regarding claim 14, Pat '941discloses the semiconductor device structure of claim 11 as described above.
Pat '941 further discloses, in claim 5, the first sidewall spacer is in contact with the metal layer (all limitations are the same with the limitations recited in claim 5 of Pat '941).
Regarding claim 15, Pat '941discloses the semiconductor device structure of claim 14 as described above.
Pat '941 further discloses, in claim 6, a second sidewall spacer in contact with the first sidewall spacer (all limitations are the same with the limitations recited in claim 6 of Pat '941).
Regarding claim 16, Pat '941discloses the semiconductor device structure of claim 15 as described above.
Pat '941 further discloses, in claim 7, a contact etch stop layer (CESL) in contact with the second sidewall spacer ("a contact etch stop layer (CESL) in contact with the second sidewall spacer and the first SAC layer", in claim 7 of Pat '941, is interpreted as the same limitation).
Regarding claim 17, Pat '941 discloses, in claim 9, a semiconductor device structure, comprising:
first and second source/drain features (all limitations are the same with the limitations recited in claim 9 of Pat '941);
a semiconductor layer disposed between and in contact with the first and second source/drain features ("a channel layer disposed between and in contact with the first and second source/drain features, wherein the channel layer is formed of a semiconductor layer", in claim 9 of Pat '941, is interpreted as the same limitation);
a gate electrode layer surrounding a portion of the semiconductor layer; an isolation layer disposed over the gate electrode layer; a metal layer disposed between and in contact with the gate electrode layer and the isolation layer; and a sidewall spacer in contact with the gate dielectric layer and the isolation layer ("a gate dielectric layer surrounding at least a surface of the channel layer; a gate electrode layer surrounding at least a surface of the gate dielectric layer; an isolation layer disposed over the gate electrode layer; a metal layer disposed between and in contact with the gate electrode layer and the isolation layer; and a first sidewall spacer in contact with the gate dielectric layer, the first SAC layer, and the isolation layer", in claim 9 of Pat '941, is interpreted as the same limitation).
Pat '941 does not explicitly disclose a gate dielectric layer in contact with the gate electrode layer.
Pat '941 teaches, in claim 1, a gate dielectric layer in contact with the gate electrode layer (all limitations are the same with the limitations recited in claim 1 of Pat '941), for the purpose of preventing damage to the gates during processing of the ICs.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in claim 9 of Pat '941 to have the gate dielectric layer in contact with the gate electrode layer, as taught by claim 1 of Pat '941, for the purpose of preventing damage to the gates during processing of the ICs.
Regarding claim 18, Pat '941 discloses the semiconductor device structure of claim 17 as described above.
Pat '941 further discloses, in claim 10, the isolation layer comprises a dielectric material free of oxygen atoms (all limitations are the same with the limitations recited in claim 10 of Pat '941).
Regarding claim 19, Pat '941 discloses the semiconductor device structure of claim 17 as described above.
Pat '941 further teaches, in claim 5, the sidewall spacer is in further contact with the metal layer ("the first sidewall spacer is in contact with the metal layer", in claim 5 of Pat '941, is interpreted as the same limitation), for the purpose of preventing damage to the gates during processing of the ICs.
Regarding claim 20, Pat '941 discloses the semiconductor device structure of claim 17 as described above.
Pat '941 does not explicitly disclose the metal layer has a thickness of about 0.5 nm to about 10 nm.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the thickness of the metal layer as claimed in claim 20 in order to optimize the performance of the device in .. It is noted that the selection dimension of the thickness of the metal layer as being no more than use of known technique to improve similar devices in the same way. See MPEP 2143 I. C. It is noted that if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond that person's skill. KSR International Co. v. Teleflex Inc., 550 US 398, 82 USPQ2d 1385, 1389 (2007). In Gardnerv.TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
The specification contains no disclosure of either the critical nature of the claimed arrangement (i.e.- the metal layer has a thickness of about 0.5 nm to about 10 nm) or any unexpected results arising therefrom.
Where patentability is said to be based upon particular chosen limitations or upon another variable recited in a claim, the applicant must show that the chosen limitations are critical. In re Woodruff, 919 F.2d 1575, 1578 (FED. Cir. 1990).
Claim 4 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,074,111 in view of Lin (US 2021/0083046).
Regarding claim 4, Pat '111 discloses the semiconductor device structure of claim 1 as described above.
Pat '111 does not explicitly disclose the first sidewall spacer is not in contact with the isolation layer.
Lin teaches, in at least figures 1B, 2R, and related text, the device comprising the first sidewall spacer (108, [26]) is not in contact with the isolation layer (180, [63]), for the purpose of reducing parasitic capacitance thereby increasing effectively the device performance ([10]).
Pat '111 and Lin are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '111 with the specified features of Lin because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '111 to have the first sidewall spacer being not in contact with the isolation layer, as taught by Lin, for the purpose of reducing parasitic capacitance thereby increasing effectively the device performance ([10], Lin).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4-10 are rejected under 35 U.S.C. 112(b)
In claim 4, lines 1-2, the limitation of “the first sidewall spacer is in contact with the isolation layer” renders the claim indefinite because the antecedent basis is unclear as to whether “the first sidewall spacer” is in contact with “the isolation layer” or not in contact with “the isolation layer” previously recited in claim 1, on at least lines 4-5. Applicant’s figure 10 used for claim 1 shows that the first sidewall spacer 33 is not in contact with the isolation layer 45. Therefore, it is suggested Applicant change “the first sidewall spacer is in contact with the isolation layer” in claim 4, lines 1-2 to “the first sidewall spacer is not in contact with the isolation layer”. For examination purposes, the limitation will be interpreted and examined as “the first sidewall spacer is not in contact with the isolation layer”. Correction is requested.
Claims 5-10 are also rejected as being dependent on claim 4.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 3-4 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Lin (US 2021/0083046).
Regarding claim 1, Lin discloses, in at least figures 1B, 2R, and related text, a semiconductor device structure, comprising:
a gate dielectric layer (114, [26]);
a gate electrode layer (116, [26]) in contact with the gate dielectric layer (114, [26]);
an isolation layer (180, [63]) disposed over the gate electrode layer (116, [26]);
a first sidewall spacer (108, [26]) in contact with the gate dielectric layer (114, [26]); and
a liner layer (176, [61]) having a first portion disposed between the isolation layer (180, [63]) and the gate electrode layer (116, [26]) and a second portion in contact with the first sidewall spacer (108, [26]).
Regarding claim 3, Lin discloses the semiconductor device structure of claim 1 as described above.
Lin further discloses, in at least figures 1B, 2R, and related text, the liner layer (176, [61]) is a dielectric layer that is free of oxygen atoms.
Regarding claim 4, Lin discloses the semiconductor device structure of claim 1 as described above.
Lin further discloses, in at least figures 1B, 2R, and related text, the first sidewall spacer (108, [26]) is not in contact with the isolation layer (180, [63]).
Claim(s) 1-4 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Bai (US 2019/0295889).
Regarding claim 1, Bai discloses, in at least figure 1 and related text, a semiconductor device structure, comprising:
a gate dielectric layer (122, [44]);
a gate electrode layer (124, [46]) in contact with the gate dielectric layer (122, [44]);
an isolation layer (140, [56]) disposed over the gate electrode layer (124, [46]);
a first sidewall spacer (126, [35]) in contact with the gate dielectric layer (122, [44]); and
a liner layer (130, [51]) having a first portion disposed between the isolation layer (140, [56]) and the gate electrode layer (124, [46]) and a second portion in contact with the first sidewall spacer (126, [35]).
Regarding claim 2, Bai discloses the semiconductor device structure of claim 1 as described above.
Bai further discloses, in at least figure 1 and related text, the liner layer (130, [51]) is further in contact with the gate dielectric layer (122, [44]).
Regarding claim 3, Bai discloses the semiconductor device structure of claim 1 as described above.
Bai further discloses, in at least figure 1 and related text, the liner layer (130, [51]) is a dielectric layer that is free of oxygen atoms.
Regarding claim 4, Bai discloses the semiconductor device structure of claim 1 as described above.
Bai further discloses, in at least figure 1 and related text, the first sidewall spacer (126, [35]) is not in contact with the isolation layer (140, [56]).
Allowable Subject Matter
Claims 5-10 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1, 4, and 5 that recite "the first sidewall spacer has a top and a sidewall in contact with the liner layer" in combination with other elements of the base claims 1, 4, and 5.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONG-HO KIM whose telephone number is (571)270-0276. The examiner can normally be reached Monday thru Friday; 8:30 AM to 5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TONG-HO KIM/Primary Examiner, Art Unit 2811
Prosecution Insights