DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/13/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 17-19 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 9-11 of U.S. Patent No. 11,652,140. Although the claims at issue are not identical, they are not patentably distinct from each other because the conflicting claims have been patented.
Regarding claim 17, Pat '140 discloses, in claim 9, a memory cell, comprising:
a first transistor comprising a first gate electrode layer ("a second transistor disposed adjacent the first transistor, wherein the second transistor includes a second gate electrode layer, a second source region, and a second drain region", in claim 9 of Pat ‘140, is interpreted as the same limitation);
a second transistor disposed adjacent the first transistor ("a first transistor including a first gate electrode layer, a first source region, and a first drain region; a second transistor disposed adjacent the first transistor", in claim 9 of Pat ‘140, is interpreted as the same limitation);
a third transistor disposed over the first transistor, wherein the third transistor comprises the first gate electrode layer ("a fourth transistor disposed over the second transistor, wherein the fourth transistor includes the second gate electrode layer, a fourth source region, and a fourth drain region", in claim 9 of Pat ‘140, is interpreted as the same limitation);
a fourth transistor disposed over the second transistor, wherein the fourth transistor comprises a second gate electrode layer ("a third transistor disposed over the first transistor, wherein the third transistor includes a third gate electrode layer, a third source region, and a third drain region", in claim 9 of Pat ‘140, is interpreted as the same limitation);
a fifth transistor disposed over the third transistor ("a sixth transistor disposed over the fourth transistor, wherein the sixth transistor includes a fourth gate electrode layer, a sixth source region, and a sixth drain region", in claim 9 of Pat ‘140, is interpreted as the same limitation); and a sixth transistor disposed over the fourth transistor, wherein the sixth transistor comprises the second gate electrode layer ("a fifth transistor disposed over the third transistor, wherein the fifth transistor includes the third gate electrode layer, a fifth source region, and a fifth drain region", in claim 9 of Pat ‘140, is interpreted as the same limitation).
Regarding claim 18, Pat '140 discloses the memory cell of claim 17 as described above.
Pat '140 further discloses, in claim 9, the second transistor comprises a third gate electrode layer, and the fifth transistor comprises a fourth gate electrode layer ("a first transistor including a first gate electrode layer, a first source region, and a first drain region; the sixth transistor includes a fourth gate electrode layer, a sixth source region, and a sixth drain region", in claim 9 of Pat ‘140, is interpreted as the same limitation).
Regarding claim 19, Pat '140 discloses the memory cell of claim 18 as described above.
Pat '140 further discloses, in claims 10 and 11, a first dielectric layer disposed between the second gate electrode layer and the third gate electrode layer, wherein the first gate electrode layer extends through the first dielectric layer ("a first passivation layer disposed between the first, second transistors and third, fourth transistors; and a first one or more conductive features electrically connecting the third gate electrode layer and the first, second, fourth drain regions " and “the second gate electrode layer extends through the first passivation layer”, in claims 10 and 11 of Pat ‘140, are interpreted as the same limitation).
Claims 1-2 and 7-9 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 17 of U.S. Patent No. 12,068,370 in view of claims 9-10 and 12-14 of U.S. Patent No. 11,652,140.
Regarding claim 1, Pat '370 discloses, in claim 17, a semiconductor device structure, comprising:
first and second source/drain epitaxial features; a first dielectric layer disposed over the first and second source/drain epitaxial features; third and fourth source/drain epitaxial features disposed over the first dielectric layer ("first, second, third, and fourth source/drain epitaxial features; a first dielectric layer disposed over the first, second, third, and fourth source/drain epitaxial features; fifth, sixth, seventh, and eighth source/drain epitaxial features disposed over the first dielectric layer", in claim 17 of Pat ‘370, is interpreted as the same limitation);
a second dielectric layer disposed over the third and fourth source/drain epitaxial features; fifth and sixth source/drain epitaxial features disposed over the second dielectric layer; and the second dielectric layer is disposed over the first gate electrode layer ("a second dielectric layer disposed over the fifth, sixth, seventh, and eighth source/drain epitaxial features and the second gate electrode layer" and “ninth, tenth, eleventh, and twelfth source/drain epitaxial features disposed over the second dielectric layer, wherein the third gate electrode is disposed between the ninth and tenth source/drain epitaxial features”, in claims 18 and 19 of Pat ‘370, are interpreted as the same limitation);
a first gate electrode layer disposed between the first and second source/drain epitaxial features, between the third and fourth source/drain epitaxial features, and through the first dielectric layer ("a second gate electrode layer disposed between the fifth and sixth source/drain epitaxial features, between the third and fourth source/drain epitaxial features, and through the first dielectric layer", in claim 17 of Pat ‘370, is interpreted as the same limitation).
Pat ‘370 does not explicitly disclose the fifth source/drain epitaxial feature is electrically connected to the first gate electrode layer.
Pat ‘140 teaches, in claim 12, the fifth source/drain epitaxial feature is electrically connected to the first gate electrode layer ("a second passivation layer disposed between the third, fourth transistors and the fourth, fifth transistors; and a second one or more conductive features electrically connecting the second gate electrode layer to the sixth drain region", in claim 12 of Pat ‘140, is interpreted as the same limitation), for the purpose of providing three- dimensional designs, such as a multi-gate field effect transistor (FET), including a nanosheet FET thereby improve integration of density.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat ‘370 to have the fifth source/drain epitaxial feature being electrically connected to the first gate electrode layer, as taught by Pat ‘140, for the purpose of providing three- dimensional designs, such as a multi-gate field effect transistor (FET), including a nanosheet FET thereby improve integration of density.
Regarding claim 2, Pat '370 in view of Pat ‘140 discloses the semiconductor device structure of claim 1 as described above.
Pat ‘140 further teaches, in claim 13, one or more first layers disposed between the first and second source/drain epitaxial features; one or more second layers disposed between the third and fourth source/drain epitaxial features; and one or more third layers disposed between the fifth and sixth source/drain epitaxial features ("a second one or more channels disposed between the second source region and the second drain region; a fourth one or more channels disposed between the fourth source region and the fourth drain region; a sixth one or more channels disposed between the sixth source region and the sixth drain region", in claim 13 of Pat ‘140, is interpreted as the same limitation), for the purpose of providing three- dimensional designs, such as a multi-gate field effect transistor (FET), including a nanosheet FET thereby improve integration of density.
Regarding claim 7, Pat '370 in view of Pat ‘140 discloses the semiconductor device structure of claim 2 as described above.
Pat ‘140 further teaches, in claims 9 and 12, a second gate electrode layer disposed over the second dielectric layer, wherein the second gate electrode layer is disposed between the fifth and the sixth source/drain epitaxial features ("a sixth transistor disposed over the fourth transistor, wherein the sixth transistor includes a fourth gate electrode layer, a sixth source region, and a sixth drain region" and “a second passivation layer disposed between the third, fourth transistors and the fourth, fifth transistors”, in claims 9 and 12 of Pat ‘140, are interpreted as the same limitation), for the purpose of providing three- dimensional designs, such as a multi-gate field effect transistor (FET), including a nanosheet FET thereby improve integration of density.
Regarding claim 8, Pat '370 in view of Pat ‘140 discloses the semiconductor device structure of claim 7 as described above.
Pat ‘140 further teaches, in claim 14, the first gate electrode layer surrounds the one or more first layers and the one or more second layers, and the second gate electrode layer surrounds the one or more third layers ("the first gate electrode layer wraps around a portion of first one or more channels, the second gate electrode layer wraps around a portion of the second one or more channels and a portion of the fourth one or more channels, the third gate electrode layer wraps around a portion of the third one or more channels and a portion of the fifth one or more channels, and the fourth gate electrode layer wraps around a portion of the sixth one or more channels", in claim 14 of Pat ‘140, is interpreted as the same limitation), for the purpose of providing three- dimensional designs, such as a multi-gate field effect transistor (FET), including a nanosheet FET thereby improve integration of density.
Regarding claim 9, Pat '370 in view of Pat ‘140 discloses the semiconductor device structure of claim 1 as described above.
Pat ‘140 further teaches, in claim 10, the first source/drain epitaxial feature is electrically connected to the third source/drain epitaxial feature ("a first one or more conductive features electrically connecting the third gate electrode layer and the first, second, fourth draiSeoln regions ", in claim 10 of Pat ‘140, is interpreted as the same limitation), for the purpose of providing three- dimensional designs, such as a multi-gate field effect transistor (FET), including a nanosheet FET thereby improve integration of density.
Claims 3-6 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 17 of U.S. Patent No. 12,068,370 in view of claims 9-10 and 12-14 of U.S. Patent No. 11,652,140, and further in view of Seol (US 2022/0077321).
Regarding claim 3, Pat '370 in view of Pat ‘140 discloses the semiconductor device structure of claim 2 as described above.
Pat '370 in view of Pat ‘140 does not explicitly disclose the one or more first layers, one or more second layers, and one or more third layers each comprises a semiconductor material.
Seol teaches, in at least figure 2 and related text, the device comprising the one or more first layers (140, [59]), one or more second layers (140, [59]), and one or more third layers (140, [59]) each comprises a semiconductor material ([12]), for the purpose of providing field effect transistor including a multi-bridge channel configuration ([6]) thereby improving density of integration.
Pat '370, Pat ‘140, and Seol are analogous art because they are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '370 in view of Pat ‘140 with the specified features of Seol because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '370 in view of Pat ‘140 to have the one or more first layers, one or more second layers, and one or more third layers each comprising a semiconductor material, as taught by Seol, for the purpose of providing field effect transistor including a multi-bridge channel configuration ([6], Seol) thereby improving density of integration.
Regarding claim 4, Pat '370 in view of Pat ‘140 discloses the semiconductor device structure of claim 2 as described above.
Pat '370 in view of Pat ‘140 does not explicitly disclose the one or more first layers, one or more second layers, and one or more third layers each comprises a two-dimensional material.
Seol teaches, in at least figure 2 and related text, the device comprising the one or more first layers (140, [59]), one or more second layers (140, [59]), and one or more third layers (140, [59]) each comprises a two-dimensional material ([12]), for the purpose of providing field effect transistor including a multi-bridge channel configuration ([6]) thereby improving density of integration.
Pat '370, Pat ‘140, and Seol are analogous art because they are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '370 in view of Pat ‘140 with the specified features of Seol because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '370 in view of Pat ‘140 to have the one or more first layers, one or more second layers, and one or more third layers each comprising a two-dimensional material, as taught by Seol, for the purpose of providing field effect transistor including a multi-bridge channel configuration ([6], Seol) thereby improving density of integration.
Regarding claim 5, Pat '370 in view of Pat ‘140 and Seol discloses the semiconductor device structure of claim 4 as described above.
Seol further teaches, in at least figure 2 and related text, the two-dimensional material comprises graphene ([12]), for the purpose of providing field effect transistor including a multi-bridge channel configuration ([6]) thereby improving density of integration.
Regarding claim 6, Pat '370 in view of Pat ‘140 and Seol discloses the semiconductor device structure of claim 4 as described above.
Seol further teaches, in at least figure 2 and related text, the two-dimensional material ([12], [85]) comprises Te2, WS2, MoS2, WSe2, or MoSe2, for the purpose of providing field effect transistor including a multi-bridge channel configuration ([6]) thereby improving density of integration.
Allowable Subject Matter
Claims 10-16 are allowed because the prior art of record neither anticipates nor render obvious the limitations of the base claims 10 that recite "a second gate electrode layer disposed between the fifth and sixth source/drain epitaxial features, between the ninth and tenth source/drain epitaxial features, and through the second dielectric layer" in combination with other elements of the base claims 10.
Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 17, 18, 19, and 20 that recite "the second gate electrode layer extends through the second dielectric layer" in combination with other elements of the base claims 17, 18, 19, and 20.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONG-HO KIM whose telephone number is (571)270-0276. The examiner can normally be reached Monday thru Friday; 8:30 AM to 5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TONG-HO KIM/Primary Examiner, Art Unit 2811
Prosecution Insights