Prosecution Insights
Last updated: August 17, 2026
Application No. 18/772,202

SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME

Final Rejection §102§Other
Filed
Jul 14, 2024
Priority
Jun 30, 2020 — divisional of 11/373,971 +2 more
Examiner
MENZ, LAURA MARY
Art Unit
2813
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
2 (Final)
88%
Grant Probability
Favorable
3-4
OA Rounds
4m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
828 granted / 946 resolved
+19.5% vs TC avg
Moderate +9% lift
Without
With
+8.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
37 currently pending
Career history
975
Total Applications
across all art units

Statute-Specific Performance

§101
3.1%
-36.9% vs TC avg
§103
27.4%
-12.6% vs TC avg
§102
40.1%
+0.1% vs TC avg
§112
7.5%
-32.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 946 resolved cases

Office Action

§102 §Other
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 3-4, 7 and 31 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Yu et al (US 2008/0173966). 1. (Currently Amended) A semiconductor device structure, comprising: one or more bonding pads (Fig.4a (140/22a) and [0021]) disposed over a substrate (Fig.4a (110) and [0021]); and a first passivation layer (Fig.4a (200) and [0022]) disposed over the one or more bonding pads(Fig.4a (140/22a) and [0021]), wherein the first passivation layer (Fig.4a (26) and [0022]) comprises: a first passivation sublayer (Fig.4a (26) and [0022]) comprising a first dielectric material, wherein the first dielectric material is a first oxide [0022], and the first passivation sublayer (Fig.4a (26) and [0022]) has a first thickness [0022]; a second passivation sublayer (Fig.4a (30/38) and [0022]) disposed over the first passivation sublayer (Fig.4a (26) and [0022]),wherein the second passivation sublayer Fig.4a (30/38) and [0022]) comprises a second dielectric material [0022]s the second dielectric material is a second oxide [0022], the second passivation sublayer (Fig.4a (30/38) and [0022]) is physically distinct from the first passivation sublayer (Fig.4a (26) and [0022]), and the second passivation sublaver has a second thickness (Fig.4a (30/38) and [0022]); and a third passivation sublayer (Fig.4a (40/50) and [0022]) disposed over the second passivation sublayer (Fig.4a (30/38) and [0022]),wherein the third passivation sublayer (Fig.4a (40) and [0022]) comprises a third dielectric material [0022], the third dielectric material is a first nitride [0022], the third passivation sublayer (Fig.4a (40/50) and [0022]) is physically distinct from the second passivation sublayer (Fig.4a (30/38) and [0022]), and the third passivation sublayer(Fig.4a (40/50) and [0022]) has a third thickness ranging from about 1000 nm to about 2000 nm [0022] different from the first and second dielectric materials [0022]. 3. (Currently Amended) The semiconductor device structure of claim [[2]] 1, wherein the first oxide is undoped silica glass (Fig.4a (26) and [0022]), and the second oxide is a high density plasma oxide (Fig.4a (30/38) and [0022], and the first nitride is silicon nitride (Fig.4a (40/50) and [0022]). 4. (Currently Amended) The semiconductor device structure of claim [[2]] 1, wherein the second thickness [0022] is substantially greater than the first thickness,[0022] and the third thickness [0022] is substantially greater than the first thickness [0022]. 7. (Original) The semiconductor device structure of claim 1, wherein the third passivation sublayer (Fig.4a (40/50) and [0022]) further comprises a trench (Fig.4b (48) and [0023].. 31. (New) The semiconductor device structure of claim 1, wherein the first nitride is a metal nitride (Fig.4a (50) and [0022]). Response to Arguments Applicant’s arguments with respect to the above claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Walter et al (US 2013/0234300); Tsai et al (US 6017614); and Hsiao (US 6277725) teach similar structures. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA M MENZ whose telephone number is (571)272-1697. The examiner can normally be reached Monday-Friday 7:00-3:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached at 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LAURA M MENZ/Primary Examiner, Art Unit 2813 7/28/26
Read full office action

Prosecution Timeline

Jul 14, 2024
Application Filed
Mar 09, 2026
Non-Final Rejection mailed — §102, §Other
May 11, 2026
Interview Requested
Jun 02, 2026
Response Filed
Jul 30, 2026
Final Rejection mailed — §102, §Other (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12706251
SEMICONDUCTOR DEVICE WITH ADVANCED PAD STRUCTURE AND METHOD FOR FORMING SAME
3y 4m to grant Granted Aug 11, 2026
Patent 12708046
SEMICONDUCTOR DEVICE INCLUDING CROSS-DIE BONDING RING AND METHODS FOR FORMING THE SAME
3y 2m to grant Granted Aug 11, 2026
Patent 12702002
DOUBLE-SIDED HEAT DISSIPATION POWER SEMICONDUCTOR MODULE AND METHOD OF MANUFACTURING THE SAME
3y 7m to grant Granted Aug 04, 2026
Patent 12701997
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE
3y 3m to grant Granted Aug 04, 2026
Patent 12701809
SEMICONDUCTOR PACKAGE INCLUDING MULTIPLE SEMICONDUCTOR CHIPS
2y 11m to grant Granted Aug 04, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
88%
Grant Probability
96%
With Interview (+8.7%)
2y 5m (~4m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 946 resolved cases by this examiner. Grant probability derived from career allowance rate.

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