Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 7, 9 objected to because of the following informalities:
Regarding claim 7, Claim 7 recites, in part “wherein the solder layer and the solder ball are provided between the substrate and the semiconductor device further comprises:”
This should read “wherein the solder layer and the solder ball provided between the substrate and the semiconductor device further comprises:”
NOTE: For examination purposes the claim will be interpreted to read, in part, “wherein the solder layer and the solder ball provided between the substrate and the semiconductor device further comprises:”
Regarding claim 9, Claim 9 recites, in part, “a manufacturing method of a semiconductor package, comprising: providing a solder layer over a plurality of contact pads of the substrate; providing a semiconductor device over a substrate.”
This may be corrected by re-writing the claim to read in part “A manufacturing method of a semiconductor package, comprising; providing a semiconductor device over a substrate providing a solder layer over a plurality of contact pads of the substrate;”
NOTE: For examination purposes the claim will be interpreted to read, in part, “A manufacturing method of a semiconductor package, comprising; providing a semiconductor device over a substrate providing a solder layer over a plurality of contact pads of the substrate;”
Claim 9 also recites, in part, “one of the solder layer and the3 plurality of solder balls comprises In;”
This should read “one of the solder layers and the plurality of solder balls comprises In;”
Appropriate correction is required.
Claim Rejections 35 U.S.C. § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 10 recites the limitation "performing a first reflow process for melting the solder layer that comprises In; " in lines 1-2. There is insufficient antecedent basis for this limitation in the claim.
Claim 10 depends from claim 9 which states, in part “one of the solder layer and the plurality of solder balls comprises In.” There is no intervening limitation that the solder layer is the one of the solder layer and solder ball that comprises indium.
For examination purposes examiner interprets this claim as reading “The manufacturing method of the semiconductor package as claimed in claim 9, wherein performing a reflow process comprises: performing a first reflow process for melting the one of the solder layer and the plurality of solder balls which comprises In; and performing a second reflow process for melting the plurality of solder balls and solder layers to form a solder joint structure bonded between the substrate and the semiconductor device.”
Examiner notes that the first reflow process causes the one of the solder layer and the solder ball which is melted to bond with the one which is not, and that the second reflow process is at a temperature sufficient to melt both solder layers and solder balls.
Claim 12 recites the limitation " the manufacturing method of the semiconductor package as claimed in claim 9, wherein central ones of the plurality of solder balls, surrounded by the outermost ones of the plurality of solder balls, are free of encapsulation of the underfill material " in lines 1-3. There is insufficient antecedent basis for this limitation in the claim.
Claim 12 depends from claim 9. Claim 9 does not recite an underfill.
For examination purposes this claim is being treated as depending from claim 11 which recites in part “providing an underfill material between the semiconductor device and the redistribution structure”
Claim 14 recites the limitation “The manufacturing method of the semiconductor package as claimed in claim 13, wherein the first reflow process is performed at a first process temperature, and the second reflow process is performed at a second process temperature higher than the first process temperature " in lines 1-4. There is insufficient antecedent basis for this limitation in the claim.
Claim 14 depends from claim 13 and through 13 from 9. Neither claim 13 nor 9 describe the reflow process as having a first and second reflow process.
For examination purposes this claim is being treated as depending from claim 10 which recites “The manufacturing method of the semiconductor package as claimed in claim 9, wherein performing a reflow process comprises: performing a first reflow process for melting the one of the solder layer and the plurality of solder balls which comprises In; and performing a second reflow process for melting the plurality of solder balls and solder layers to form a solder joint structure bonded between the substrate and the semiconductor device.” as described above.
Double Patenting Rejection
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 and 14 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 16-20 of U.S. Patent No. 12107064. Although the claims at issue are not identical, they are not patentably distinct from each other because of the reasons below.
Claims of the Instant Application 18772304
Claims of US Patent 12107064
2
16
16 Although the ‘7064 patent does not explicitly recite "wherein a solder layer and a solder ball are provided between the substrate and the semiconductor device" it does recite providing a semiconductor layer over the substrate, after reciting providing a solder layer and a solder ball over the substrate.
14
16 Although the ‘7064 patent does not explicitly recite "wherein the semiconductor device is mounted with a plurality of solder balls provided over substrate it does recite providing a solder layer and a solder ball over the substrate
A terminal disclaimer may be effective to overcome a nonstatutory double patenting rejection over a reference patent (37 CFR 1.321(b) and (c)). A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional, the reply must be complete. MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/PatentForms. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/TerminalDisclaimer.
Claim Rejections 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4, 7-10, and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US Pub. 20140001645), hereinafter referred to as Lin, Kim et al. (KR 101133126 B1), hereinafter referred to as Kim, and Choudry et al. (US Pub. 20220324063), hereinafter referred to as Choudry.
Regarding claim 1, Lin teaches a manufacturing method of a semiconductor package, comprising: providing a semiconductor device (Lin, 903, Fig. 9A, para. 41) over a substrate (Lin, 202, 204, Fig. 9A, para. 16, 202 and 204 are the sides of substrate 205 which is not explicitly labeled in Fig. 9A), wherein a solder ball is provided between the substrate and the semiconductor device (Lin, 803, Fig. 9A, para. 38) and performing a reflow process for melting the solder balls to form a solder joint structure bonded between the substrate and the semiconductor device (Lin, para. 44).
Lin does not teach wherein a solder layer and a solder ball are provided between the substrate and the semiconductor device, and at least one of the solder layer and the solder ball comprises In; performing a first reflow process for melting the one of the solder layer and the solder ball that comprises In.
However, Kim teaches a method of manufacturing a semiconductor package wherein there is a solder layer (Kim, 15, Fig. 2d) disposed beneath a solder ball (Kim, 17, Fig. 2d) which are merged during a reflow process (Kim, Fig. 2e) before the combined solder ball is used to connect the substrate to a device.
Therefore it would have been obvious to a person having ordinary skill in the art before the filing date of the invention to combine the technique of Kim with the method of Kim to perform an initial bonding between the solder layer and solder ball of Kim in order to reduce the thermal stress on the intermetallic compound (IMC) layer (Kim, Background, para. 4).
Additionally, Choudry teaches a solder alloy that contains 5-6% of Indium by weight (Choudry, para. 140).
Therefore, it would have been obvious to one having ordinary skill in the art before the filing date of the invention to utilize the solder alloy of Choudry in order to improve mechanical properties and decrease the solidus and liquidus temperatures (Choudry, para. 48) and to provide one of the two components with a lower melting temperature such that the first reflow process causes reduced thermal stress (Kim, Background, para. 4).
Regarding claim 2, modified Lin teaches the manufacturing method of the semiconductor package as claimed in claim 1, wherein the first reflow process is performed at a first process temperature (Choudry para. 140, the indium pportions have a melting temperature between 195.1 °C and 211.8°C),
and the second reflow process is performed at a second process temperature higher than the first process temperature (Choudry, para. 147, teaches an indium free solder alloy, melting temperature between 221.9 °C -229.3 °C).
Regarding claim 3, modified Lin teaches the manufacturing method of the semiconductor package as claimed in claim 1, wherein the first process temperature ranges from 120°C to 224°C (Choudry, para. 140).
Regarding claim 4, modified Lin teaches the manufacturing method of the semiconductor package as claimed in claim 1, wherein the second process temperature ranges from 220°C to 260°C (Choudry, para. 147).
Regarding claim 7, modified Lin teaches the manufacturing method of the semiconductor package as claimed in claim 1, wherein the solder layer and the solder ball provided between the substrate and the semiconductor device further comprises: providing the solder layer on a plurality of contact pads of the substrate (Kim, 14, Fig. 2d); and mounting the solder ball on an active surface of the semiconductor device and bonded to the substrate (Lin, 803, Fig. 9A, para. 44).
Regarding claim 8, modified Lin teaches the manufacturing method of the semiconductor package as claimed in claim 1, but does not explicitly wherein the solder layer comprises indium, and the solder ball is free of indium.
However, Kim shows the solder ball being reflowed (Kim, 2e), thus it has the lower melting temperature caused by the indium, however, it would have been obvious to try an alternate arrangement wherein the solder layer has the lower melting temperature and thus contains the indium. Having the lower melting temperature in the solder layer (Kim, 15, Fig. 2d) would help to reduce thermal stress on the pad (Kim, 14, Fig. 2D).
Regarding claim 9, Lin teaches a manufacturing method of a semiconductor package, comprising: providing a semiconductor device (Lin, 903, Fig. 9A, para. 41) over a substrate (Lin, 202, 204, Fig. 9A, para. 16, 202 and 204 are the sides of substrate 205 which is not explicitly labeled in Fig. 9A), wherein the semiconductor device is mounted with a plurality of solder balls (Lin, 803, Fig. 9A, para. 38) provided over substrate, and performing a reflow process on the solder ball to form a solder joint structure bonded between the substrate and the semiconductor device (Lin, para. 44).
Lin does not teach providing a solder layer over a plurality of contact pads of the substrate; one of the solder layer and the plurality of solder balls comprises In, wherein the reflow process is performed on the solder layer and solder ball to form a solder joint structure bonded between the substrate and the semiconductor device, or wherein the solder joint structure comprises, by weight percent, 2% to 23% of In.
However, However, Kim teaches a method of manufacturing a semiconductor package wherein there is a solder layer (Kim, 15, Fig. 2d) disposed beneath a solder ball (Kim, 17, Fig. 2d) which are merged during a reflow process (Kim, Fig. 2e) before the combined solder ball is used to connect the substrate to a device.
Therefore it would have been obvious to a person having ordinary skill in the art before the filing date of the invention to combine the technique of Kim with the method of Kim to perform an initial bonding between the solder layer and solder ball of Kim in order to reduce the thermal stress on the intermetallic compound (IMC) layer (Kim, Background, para. 4).
Additionally, Choudry teaches a solder alloy that contains 5-6% of Indium by weight (Choudry, para. 140).
Therefore, it would have been obvious to one having ordinary skill in the art before the filing date of the invention to utilize the solder alloy of Choudry in order to improve mechanical properties and decrease the solidus and liquidus temperatures (Choudry, para. 48) and to provide one of the two components with a lower melting temperature such that the first reflow process causes reduced thermal stress (Kim, Background, para. 4).
Regarding claim 10, modified Lin teaches the manufacturing method of the semiconductor package as claimed in claim 9, wherein performing a reflow process comprises: performing a first reflow process for melting the one of the solder layer and the plurality of solder balls which comprises In (Kim 2d-2e, demonstrates a first reflow process to merge the solder ball and solder layer before the reflow process to connect the semiconductor device to the substrate, which would be obvious to do using the indium bearing component since the lower temperature would produce less thermal stress, Kim, Background para. 4); and performing a second reflow process for melting the plurality of solder balls and solder layers to form a solder joint structure bonded between the substrate and the semiconductor device (Lin, 201, 803, 901, 903, Fig. 9A, para. 44).
Regarding claim 14, modified Lin teaches the manufacturing method of the semiconductor package as claimed in claim 10, wherein the first reflow process is performed at a first process temperature (Choudry para. 140, Choudry teaches an Indium containing solder that has a melting temperature of 195.1 °C to 211.8 °C), and the second reflow process is performed at a second process temperature higher than the first process temperature (Choudry, para. 147, Choudry teaches an indium free solder with a melting temperature of 221.9 °C to 229.3 °C, using the lower melting temperature for the first reflow process to bond the solder layer and solder ball as seen in Kim Fis. 2d-2e would be obvious in order to reduce thermal stress on the components, Kim, background para. 4).
Regarding claim 15, modified Lin teaches the manufacturing method of the semiconductor package as claimed in claim 9, does not explicitly teach wherein the solder layer comprises indium, and each of the plurality of solder balls is free of indium.
However, Kim (Kim Figs 2d-2e) teaches a first reflow process to bond the solder layer and solder ball together. Choudry (Choudry paras. 140, 147) teaches solder with different melting temperatures,
Therefore, it would have been obvious to one of ordinary skill in the art before the filing date of the invention to use the lower melting temperature solder to perform the first reflow to reduce thermal stress (Kim, Background, para. 4). The solder ball containing the lower melting temperature solder or the solder layer containing the lower melting temperature alloy are obvious variants of each other.
Regarding claim 16, modified Lin teaches the manufacturing method of the semiconductor package as claimed in claim 9, but does not explicitly teach wherein each of the plurality of solder balls comprises indium, and the solder layer is free of indium.
However, Kim (Kim Figs 2d-2e) teaches a first reflow process to bond the solder layer and solder ball together. Choudry (Choudry paras. 140, 147) teaches solder with different melting temperatures,
Therefore, it would have been obvious to one of ordinary skill in the art before the filing date of the invention to use the lower melting temperature solder to perform the first reflow to reduce thermal stress (Kim, Background, para. 4). The solder ball containing the lower melting temperature solder or the solder layer containing the lower melting temperature alloy are obvious variants of each other.
Claims 17, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin and Choudry.
Regarding claim 17, Lin teaches a semiconductor package, comprising: an integrated substrate structure (Lin, 202, 204, Fig. 9A, para. 16, NOTE: 202 and 204 are the sides of substrate 205 which is not explicitly labeled in Fig. 9A), and comprises a plurality of local interconnects (Lin, 701, Fig. 8, para. 37), an encapsulating material (Lin, 905, Fig. 9B, para. 50) encapsulating the plurality of local interconnects, a front side redistribution structure (Lin, 801, Fig 8, para. 38) disposed on the plurality of local interconnects and the encapsulating material; a plurality of solder joint structures (Lin, 803, Fig. 9A, para. 38) bonded over the front side redistribution structure, and an interconnect structure (Lin, 903, Fig 9A, para. 41, Semiconductor die 903 may contain contact pads, which are a form of interconnect structure).is bonded to the integrated substrate structure through the plurality of solder joint structures.
Lin does not teach wherein the solder joint structure comprises, by weight percent, 2% to 23% of In.
However, Choudry teaches a solder material that is 5-6% Indium by weight (Choudry, para. 140).
Therefore, it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the structure of Lin with the solder of Choudry in order to improve mechanical properties and decrease the solidus and liquidus temperatures (Choudry, para. 48).
Regarding claim 19, modified Lin teaches the semiconductor package as claimed in claim 17, further comprising a plurality of semiconductor devices (Lin, 1022, Fig. 10, para. 54, Lin states 1022 may be a printed circuit board) bonded to a back side redistribution structure of the integrated substrate structure.
Regarding claim 20, modified Lin teaches the semiconductor package as claimed in claim 17, wherein the interconnect structure comprises a core substrate and a plurality of routing structures disposed on two opposite sides of the core substrate (Lin, para. 41, teaches that 903 may contain active devices, metallization layers, and contact pads (all of which are not shown for clarity) similar to the first semiconductor die 201 and the second semiconductor die 203). Device 201 is described as containing core substrate (Lin, 205, Fig. 2, para. 14), and interconnects (Lin, 701, 217, Fig. 8, paras. 59, 52).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Li and Choudry as applied to claim 17 above, and further in view of Shi et al. (US. Pub. 20200343210) hereinafter referred to as Shi.
Regarding claim 18, modified Lin teaches the semiconductor package as claimed in claim 17, further comprising an underfill material (Lin, 905, Fig. 9B, para. 50) disposed between the integrated substrate structure and the interconnect structure and encapsulating outermost ones of the plurality of solder joint structures.
Modified Lin does not teach wherein central ones of the plurality of solder joint structures surrounded by the outermost ones of the plurality of solder joint structures are free of encapsulation of the underfill material.
However, Shi teaches a method of processing an electronic package wherein the underfill layer includes a dispensing area (Shi, 2041, Fig. 3, 401, Fig. 4, paras. 41, 50)) and a non-dispensing area (Shi, 2042, Fig. 3, 402, Fig. 4, paras. 41, 50). The dispensing area is the outer portion of the underfill area, and the non-dispensing area is an inner area is which not contain underfill.
Therefore, it would have been obvious to one having ordinary skill in the art to combine the processing method of Shi with the structure of modified Lin in order to improve temperature variation reliability (Shi, para. 50).
Allowable Material
Claims 5, 6, and 11-13 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 5, modified Lin teaches the manufacturing method of the semiconductor package as claimed in claim 1, but does not teach, nor does the prior art of record suggest further comprising: before the second reflow process is performed, providing an underfill material between the semiconductor device and the redistribution structure, wherein the underfill material at least partially encapsulates the solder layer and the solder ball.
While both Lin and Shi demonstrate an underflow layer being added, in both cases the layer is added after the reflow process which couples the substrate to the semiconductor device.
Regarding claim 6, modified Lin teaches the manufacturing method of the semiconductor package as claimed in claim 1, but does not teach, nor does the prior art of record suggest wherein a weight ratio of the solder layer to the solder ball ranges from 0.1 to 1.2.
Kim teaches the solder layer (Kim, 15, Fig. 4d) and the solder ball (Kim, 17, Fig. 2d), but remains mute on their respective weights.
Regarding claim 11, modified Lin teaches the manufacturing method of the semiconductor package as claimed in claim 10, but does not teach further comprising: after the first reflow process and before the second reflow process is performed, providing an underfill material between the semiconductor device and the redistribution structure, wherein the underfill material encapsulates outermost ones of the plurality of solder balls and the corresponding solder layer.
While both Lin and Shi demonstrate an underflow layer being added, in both cases the layer is added after the reflow process which couples the substrate to the semiconductor device.
Claim 12 is allowed as depending from allowed claim 11.
Regarding claim 13, modified Lin teaches the manufacturing method of the semiconductor package as claimed in claim 9, but does not teach wherein a weight ratio of the solder layer on one of the plurality of contact pads to one of the plurality of solder balls ranges from about 0.1 to about 1.2.
Kim teaches the solder layer (Kim, 15, Fig. 4d) and the solder ball (Kim, 17, Fig. 2d), but remains mute on their respective weights.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Liu (US Pub. 20230063304) teaches a method of fabricating a semiconductor device wherein there is a semiconductor device disposed over a substrate and connected by solder balls and pads.
We (US Pub. 20160329284) teaches a semiconductor device wherein an underfill layer is used to encapsulate interconnections.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIERAN M CUNNINGHAM whose telephone number is (571)272-9654. The examiner can normally be reached Mon-Fri 8:30-5:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 5712703042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KIERAN M. CUNNINGHAM/ Examiner, Art Unit 2893
/Britt Hanley/ Supervisory Patent Examiner, Art Unit 2893
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