DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
The 6/1/2026 "Reply" elects without traverse and identifies claims 1-2 and 4-13 as being drawn to Invention I, Species B. Accordingly, Examiner has withdrawn claims 3 and 14-20 from further consideration as being drawn to a non-elected invention. See, for example, 37 CFR § 1.142(b).
The 4/22/2026 restriction requirement is proper, is maintained, and is hereby made final.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 6-10, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Chiu (US Pub. No. 2023/0145518) in view of Chen (US Pub. No. 2021/0159160).
Regarding claim 1, in FIG. 15, Chiu discloses a semiconductor stack structure, comprising: a first semiconductor element (100A’, paragraph [0063]); a second semiconductor element (100B’) side-by-side bonded to the first semiconductor element through a direct bonding manner (hybrid bonding, paragraph [0057]); a printed circuit board (acting as a package substrate) (150’), wherein the first semiconductor element and the second semiconductor element are bonded on (or in contact with) the printed circuit board; and a fourth semiconductor element (100C’) bonded on (or in contact with) the first semiconductor element and the second semiconductor element.
Chiu appears not to explicitly disclose a third semiconductor element, wherein the first semiconductor element and the second semiconductor element are bonded on the third semiconductor element.
In paragraph [0004], Chen discloses that passive silicon interposers have replaced printed circuit boards as package substrates due to limitations with material structuring resolution to sustain device scaling and associated performance requirements.
To improve device scaling and associated performance requirements it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to replace the Chiu disclosed printed circuit board with a passive silicon interposer. In doing so, a third semiconductor element, wherein the first semiconductor element and the second semiconductor element are bonded on the third semiconductor element is formed.
Regarding claim 2, in FIG. 15, Chiu discloses that the direct bonding manner comprises a fusion bonding manner (metal to metal bond, paragraph [0057]).
Regarding claim 6, in FIG. 15, Chiu discloses that a sidewall surface of the first semiconductor element and a sidewall surface of the second semiconductor element are respectively aligned with sidewall surfaces of the third semiconductor element.
Regarding claim 7, in FIG. 15, Chiu discloses that a sidewall surface of the first semiconductor element (100A’) and a sidewall surface of the second semiconductor element (100B’) are respectively aligned (parallel) with sidewall surfaces of the fourth semiconductor element.
Regarding claim 8, in FIG. 15, Chiu discloses a semiconductor stack structure, comprising: a first semiconductor element (100A’) having a first sidewall surface (leftmost side) and a second sidewall surface (rightmost side) opposite to the first sidewall surface, wherein the first sidewall surface and the second sidewall surface have different configurations; a second semiconductor element (100B’) having a third sidewall (leftmost side) surface and a fourth sidewall (rightmost side) surface opposite to the third sidewall surface, wherein the third sidewall surface and the fourth sidewall surface have different configurations, the third sidewall surface is bonded to the second sidewall surface; a printed circuit board (acting as a package substrate) (150’), wherein the first semiconductor element and the second semiconductor element are bonded on the printed circuit board; and a fourth semiconductor element (100C’) bonded on (or in contact with) the first semiconductor element and the second semiconductor element.
Chiu appears not to explicitly disclose a third semiconductor element, wherein the first semiconductor element and the second semiconductor element are bonded on the third semiconductor element. In paragraph [0004], Chen discloses that passive silicon interposers have replaced printed circuit boards as package substrates due to limitations with material structuring resolution to sustain device scaling and associated performance requirements.
To improve device scaling and associated performance requirements it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to replace the Chiu disclosed printed circuit board with a passive silicon interposer. In doing so, a third semiconductor element is formed, wherein the first semiconductor element and the second semiconductor element are bonded on the third semiconductor element.
Regarding claim 9, in FIG. 15, Chiu discloses the second sidewall surface and the third sidewall surface are dielectric sidewall surfaces (130 portion, paragraph [0044]) and the third sidewall surface is bonded to the second sidewall surface through a fusion bonding manner (metal to metal bond, paragraph [0057]).
Regarding claim 10, in FIG. 15, Chiu discloses that the first sidewall surface (leftmost side of 100A’) and the fourth sidewall surface (rightmost side of 100B’) are respectively aligned (or parallel with) with sidewall surfaces of the third semiconductor element (150’).
Regarding claim 13, in FIG. 15, Chiu discloses that the first sidewall surface (leftmost side of 100A’) and the fourth sidewall surface (rightmost side of 100B’) are respectively aligned (or parallel with) with sidewall surfaces of the fourth semiconductor element (100C’).
Claims 4 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Chiu (US Pub. No. 2023/0145518) in view of Chen (US Pub. No. 2021/0159160) as applied to claim 1 above, and further in view of Dutta (US Pub. No. 2023/0092429).
Regarding claims 4 and 11, the combination of Chiu and Chen appears not to explicitly disclose that bottom surfaces of the first semiconductor element and the second semiconductor element are bonded to a top surface of the third semiconductor element through a fusion bonding manner or a hybrid bonding manner.
The art however well recognized a hybrid bond between bottom surfaces of semiconductor elements and a top surface of a semiconductor element to be suitable for use in bonding the bottom surfaces of semiconductor elements to a top surface of a semiconductor element. See, for example, Dutta, paragraph [0033].
According to well-established patent law precedents (see, for example, M.P.E.P. § 2144.07), therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have hybrid bonded bottom surfaces of the first semiconductor element and the second semiconductor element to a top surface of the third semiconductor element for its recognized suitability in bonding the bottom surfaces of semiconductor elements to a top surface of a semiconductor element.
Allowable Subject Matter
Claims 5 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUCKER J WRIGHT whose telephone number is (571)270-3234. The examiner can normally be reached 8:30am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TUCKER J WRIGHT/ Primary Examiner, Art Unit 2891
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