Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamazaki et al. (US 2018/0012739).
Regarding claim 1, Yamazaki discloses an integrated chip [Figs. 13A-14D], comprising:
a gate electrode (106/206) over a substrate (102) [Fig. 13B and 14B];
a gate dielectric layer (104) over the gate electrode [Fig. 13B and 14B];
a multilayer semiconductor structure (108) over the gate dielectric layer [Fig. 13B and 14B], wherein the multilayer semiconductor structure (108) has a plurality of metal oxides (108_2), including a first metal oxide (002, e.g. indium oxide) having a highest bond energy amongst the plurality of metal oxides (002, zinc oxide) [Figs. 8, 13D and 14D; and paragraph 0230]; and
a source contact and a drain contact (112a/112b) over the multilayer semiconductor structure [Figs. 13B and 14B];
wherein the multilayer semiconductor structure (108) comprises a layer of the first metal oxide (108_3) separating a remainder of the multilayer semiconductor structure from the source contact and the drain contact [Figs. 13B and 14B].
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,114,507. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant claims are broader and therefore anticipated by the patent claims.
Regarding claim 1, U.S. Patent No. 12,114,507 discloses an integrated chip [Claims 2 and 15-17], comprising:
a gate electrode over a substrate [Claim 15];
a gate dielectric layer over the gate electrode [Claim 15];
a multilayer semiconductor structure over the gate dielectric layer [Claim 15], wherein the multilayer semiconductor structure has a plurality of metal oxides, including a first metal oxide (In-O) having a highest bond energy amongst the plurality of metal oxides (zinc oxide) [Claims 15 and 17]; and
a source contact and a drain contact over the multilayer semiconductor structure [Claim 15];
wherein the multilayer semiconductor structure comprises a layer of the first metal oxide separating a remainder of the multilayer semiconductor structure from the source contact and the drain contact [claims 16-17].
Regarding claim 2, U.S. Patent No. 12,114,507 discloses wherein the plurality of metal oxides includes zinc oxide, indium oxide, and gallium oxide, and wherein the first metal oxide corresponds to the gallium oxide [Claims 15-17].
Regarding claim 3, U.S. Patent No. 12,114,507 discloses a metal cap structure overlying and directly contacting the layer of the first metal oxide, laterally between the source contact and the drain contact [Claims 15-16].
Regarding claim 4, U.S. Patent No. 12,114,507 discloses wherein the metal cap structure comprises aluminum and calcium [Claim 15].
Regarding claim 5, U.S. Patent No. 12,114,507 discloses wherein the plurality of metal oxides further comprise a second metal oxide and a third metal oxide, wherein the multilayer semiconductor structure further comprises a mix layer between the layer of the first metal oxide and the gate dielectric layer, and wherein the mix layer comprises a mixture of the first metal oxide, the second metal oxide, and the third metal oxide [Claims 15-17].
Regarding claim 6, U.S. Patent No. 12,114,507 discloses wherein the plurality of metal oxides further comprise a second metal oxide and a third metal oxide, and wherein the multilayer semiconductor structure comprises: a cocktail layer overlying the gate dielectric layer, wherein the cocktail layer comprises a mixture of the first metal oxide and the second metal oxide; and a layer of the third metal oxide overlying and directly contacting the cocktail layer, wherein the layer of the first metal oxide overlies the layer of the third metal oxide [Claims 15-17].
Regarding claim 7, U.S. Patent No. 12,114,507 discloses wherein the plurality of metal oxides further comprise a second metal oxide and a third metal oxide, and wherein the multilayer semiconductor structure comprises: an additional layer of the first metal oxide overlying the gate dielectric layer; a layer of the third metal oxide overlying and directly contacting the additional layer of the first metal oxide; and a layer of the second metal oxide overlying and directly contacting the layer of the third metal oxide, wherein the layer of the first metal oxide overlies the layer of the second metal oxide [Figs. 15-17].
Regarding claim 8, U.S. Patent No. 12,114,507 discloses an integrated chip [Claims 11 and 15-17], comprising:
a gate electrode over a substrate [Claim 15];
a gate dielectric layer overlying the gate electrode [Claim 15];
an active structure overlying the gate dielectric layer and comprising a first cocktail layer and a first active layer (zinc oxide) overlying the first cocktail layer, wherein the first cocktail layer comprises a first semiconductor material and a second semiconductor material that are intermixed, and wherein the first active layer comprises a third semiconductor material [Claims 15-17];
a source contact and a drain contact over the active structure [Claim 15]; and
a metal cap structure overlying and directly contacting the active structure and between the source contact and the drain contact [Claims 15-17].
Regarding claim 9, U.S. Patent No. 12,114,507 discloses wherein the metal cap structure has a higher affinity for oxygen than the active structure (e.g. aluminum) [Claim 15].
Regarding claim 10, U.S. Patent No. 12,114,507 discloses wherein the first active layer (zinc oxide) has higher crystallinity than the first cocktail layer [Claims 11 and 15].
Regarding claim 11, U.S. Patent No. 12,114,507 discloses wherein the first cocktail layer comprises a first material region that is continuous and a plurality of second material regions spaced from each other and scattered in the first material region, wherein the first and second material regions correspond to the first semiconductor material and the second semiconductor material, and wherein the first semiconductor material (Indium) has a higher bond energy than the second semiconductor material (gallium) [Claim 15].
Regarding claim 12, U.S. Patent No. 12,114,507 discloses wherein each one of the first, second, and third semiconductor materials has a different metal element than each other one of the first, second, and third semiconductor materials [Claim 15-16].
Regarding claim 13, U.S. Patent No. 12,114,507 discloses wherein the active structure comprises a plurality of cocktail layers, including the first cocktail layer, and further comprises a plurality of active layers (zinc oxide), including the first active layer, and wherein the plurality of cocktail layers and the plurality of active layers are alternately stacked away from the gate dielectric layer towards the metal cap structure [Claims 15-16].
Regarding claim 14, U.S. Patent No. 12,114,507 discloses wherein the active structure comprises a diffusion region directly under the metal cap structure, and wherein the diffusion region comprises oxide of a metal material in the metal cap structure [claim 2].
Regarding claim 15, U.S. Patent No. 12,114,507 discloses wherein the gate electrode, the gate dielectric layer, and the active structure share a common width [Claim 20].
Claims 8-9, 14 and 16-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,729,990. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant claims are broader and therefore anticipated by the patent claims.
Regarding claims 8-9, U.S. Patent No. 11,729,990 discloses wherein the metal cap structure has a higher affinity for oxygen than the active structure (e.g. aluminum) [Claim 8].
Regarding claim 14, U.S. Patent No. 11,729,990 discloses wherein the active structure comprises a diffusion region directly under the metal cap structure, and wherein the diffusion region comprises oxide of a metal material in the metal cap structure [claim 11].
Regarding claim 16, U.S. Patent No. 11,729,990 discloses a method [claims 16-20], comprising:
forming a gate electrode over a substrate [claim 16];
depositing a gate dielectric layer over the gate electrode [claim 16];
forming a semiconductor channel structure (active structure) overlying the gate dielectric layer [claim 16], wherein the forming of the semiconductor channel structure comprises:
depositing a cocktail layer overlying the gate dielectric layer and comprising a first metal oxide and a second metal oxide that are intermixed [claim 17];
depositing an active layer overlying the cocktail layer and comprising a third metal oxide [claim 17];
forming a metal cap structure overlying and directly on the semiconductor channel structure [claim 16]; and
forming a source contact and a drain contact overlying the semiconductor channel structure, respectively on opposite sides of the metal cap structure [claim 16].
Regarding claim 17, U.S. Patent No. 11,729,990 discloses wherein the metal cap structure is formed on a portion of the semiconductor channel structure, and wherein the forming of the metal cap structure increases charge mobility at the portion of the semiconductor channel structure [claims 16-17].
Regarding claim 18, U.S. Patent No. 11,729,990 discloses wherein the depositing of the cocktail layer comprises:
arranging the substrate within a process chamber ]Claim 17];
adding a precursor mixture vapor into the process chamber, wherein the precursor mixture vapor comprises a first precursor vapor and a second precursor vapor mixed with the first precursor vapor, and wherein first precursor vapor and the second precursor vapor comprise individual metal elements corresponding to the first metal oxide and the second metal oxide [Claim 17]; and
adding an oxygen vapor into the process chamber, such that oxygen of the oxygen vapor reacts with the precursor mixture vapor [Claim 17].
Regarding claim 19, U.S. Patent No. 11,729,990 discloses wherein the forming of the semiconductor channel structure further comprising: depositing an additional active layer overlying the active layer, wherein the additional active layer comprises the first metal oxide and is devoid of the second metal oxide, and wherein the metal cap structure directly contacts the additional active layer [Claim 17].
Regarding claim 20, U.S. Patent No. 11,729,990 discloses wherein the source contact and the drain contact are formed after the forming of the metal cap structure [claim 16].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE R DIAZ whose telephone number is (571)272-1727. The examiner can normally be reached Monday-Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Jose R Diaz/Primary Examiner, Art Unit 2815
Prosecution Insights