DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/15/2024 was filed before the first action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5 and 7-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ker et al. (2002/0181177).
Re claim 1, Ker teaches a structure (Figs. 8-11), comprising: a substrate (82) electrically coupled to a reference voltage supply (VSS, Figs. 8-11); a first well region (86, 88) in the substrate (82); a second well region (84) in the first well region (86, 88); a contact region (VDD / N+) in the first well region (86, 88); and
an interconnect structure (“power line, ground line”, [41-44]) electrically coupled to the contact region ([39-43], Figs. 8-11), wherein the interconnect structure comprises a plurality of metallization layers (“power line, ground line”, [41-44]) electrically coupled to the reference voltage supply (VSS, [39-43], Figs. 8-11).
Re claim 2, Ker teaches the structure of claim 1, wherein the second well region (84) comprises a first source/drain (S/D) region (S) and a second S/D region (D), the structure further comprising a gate structure (VG, Mn6) above the second well region (84) and between the first (S) and second (D) S/D regions. Re claim 3, Ker teaches the structure of claim 2, further comprising a third well region (80) adjacent to the first well region (86, 88) and comprising a third S/D region (S) spaced apart from a nearest one of the first (S) and second (D) S/D regions.
Re claim 5, Ker teaches the structure of claim 3, wherein the third well region (80) comprises a p-well region (Fig. 10).
Re claim 7, Ker teaches the structure of claim 1, wherein the reference voltage supply is ground (VSS, [08, 39, 41]).
Re claim 8, Ker teaches the structure of claim 1, wherein the first well region (86, 88) comprises a deep n-well region (88).
Re claim 9, Ker teaches the structure of claim 1, wherein the second well region (84) comprises a p-well region (Fig. 10). Claim(s) 10-11, 13 and 15-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ker et al. (2002/0181177). Re claim 10, Ker teaches a structure (Fig. 10), comprising: a first well region (86, 88) in a substrate (82); a second well region (84) in the first well region (86, 88) and comprising a first source/drain (S/D) region (S) and a second S/D region (D); a gate structure (Mn6, VG) above the second well region (84) and between the first (S) and second S/D regions (D); a contact region (VDD/N+) in the first well region (86, 88); and an interconnect structure (“power line, ground line”, [41-44]) electrically coupled to the contact region ([39-43], Figs. 8-11), wherein the interconnect structure comprises a plurality of metallization layers (“power line, ground line”, [41-44]) electrically coupled to the reference voltage supply (VSS, [39-43], Figs. 8-11).
Re claim 11, Ker teaches the structure of claim 10, further comprising a third well region (80) adjacent to the first well region (86, 88) and comprising a third S/D region (S) spaced apart from a nearest one of the first (S) and second (D) S/D regions.
Re claim 13, Ker teaches the structure of claim 11, wherein the third well region (80) comprises a p-well region (Fig. 10).
Re claim 15, Ker teaches the structure of claim 10, wherein the second well region (84) comprises a p-well region (Fig. 10).
Re claim 16, Ker teaches the structure of claim 10, wherein the reference voltage supply is ground (VSS, [08, 39, 41]).
Claim(s) 17-18 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ker et al. (2002/0181177). Re claim 17, Ker teaches a method (Figs. 8-11), comprising: forming a substrate (82) electrically coupled to a reference voltage supply (VSS, Figs. 8-11); forming a first well region (86, 88) in the substrate (82); forming a second well region (84) in the first well region (86, 88); forming a contact region (VDD / N+) in the first well region (86, 88); and electrically coupling an interconnect structure (“power line, ground line”, [41-44]) electrically coupled to the contact region ([39-43], Figs. 8-11), wherein the interconnect structure comprises a plurality of metallization layers (“power line, ground line”, [41-44]) electrically coupled to the reference voltage supply (VSS, [39-43], Figs. 8-11).
Re claim 18, Ker teaches the method of claim 17, further comprising: forming a third well region (80) adjacent to the first well region (86, 88), wherein the third well region (80) comprises a third S/D region (S) spaced apart from a nearest one of a first source/drain (S/D) region (S) and a second S/D region (D) in the second well region (84).
Re claim 20, Ker teaches the method of claim 17, wherein electrically coupling the interconnect structure (“power line, ground line”, [41-44]) to the contact region ([39-43], Figs. 8-11) comprises electrically coupling the plurality of metallization layers to ground (VSS, [08, 39, 41]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 is rejected under 35 U.S.C. 103 as being unpatentable over Ker et al. (2002/0181177) in view of the following reasons.
Re claim 4, Ker teaches the structure of claim 3.
Ker does not explicitly teach wherein the third S/D region is spaced apart from the nearest one of the first and second S/D regions by a distance less than about 3 µm.
However, Applicant has not shown wherein the third S/D region is spaced apart from the nearest one of the first and second S/D regions by a distance less than about 3 µm has a specific, disclosed criticality that is unexpected and would not have been determined through routine experimentation of one having ordinary skill in the art. Therefore, it would have been obvious to adjust the spacing so as to customize, optimize, or otherwise meet customer space and design requirements, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Claim(s) 12 is rejected under 35 U.S.C. 103 as being unpatentable over Ker et al. (2002/0181177) in view of the following reasons.
Re claim 12, Ker teaches the structure of claim 11.
Ker does not explicitly teach wherein the third S/D region is spaced apart from the nearest one of the first and second S/D regions by a distance less than about 3 µm.
However, Applicant has not shown wherein the third S/D region is spaced apart from the nearest one of the first and second S/D regions by a distance less than about 3 µm has a specific, disclosed criticality that is unexpected and would not have been determined through routine experimentation of one having ordinary skill in the art. Therefore, it would have been obvious to adjust the spacing so as to customize, optimize, or otherwise meet customer space and design requirements, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Claim(s) 19 is rejected under 35 U.S.C. 103 as being unpatentable over Ker et al. (2002/0181177) in view of the following reasons.
Re claim 19, Ker teaches the method of claim 18.
Ker does not explicitly teach region from the nearest one of the first and second S/D regions by a distance less than about 3 µm.
However, Applicant has not shown wherein the third S/D region is spaced apart from the nearest one of the first and second S/D regions by a distance less than about 3 µm has a specific, disclosed criticality that is unexpected and would not have been determined through routine experimentation of one having ordinary skill in the art. Therefore, it would have been obvious to adjust the spacing so as to customize, optimize, or otherwise meet customer space and design requirements, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Allowable Subject Matter
Claims 6 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Re claim 6, Ker teaches the structure of claim 2, yet remains explicitly silent to wherein the first well region, the second well region, the first S/D region, the second S/D region, and the gate structure form portions of a p-type transistor.
Re claim 14, Ker teaches the structure of claim 10, yet remains explicitly silent to wherein the first well region, the second well region, the first S/D region, the second S/D region, and the gate structure form portions of a p-type transistor.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM S BOWEN whose telephone number is (571)272-3984. The examiner can normally be reached M-F 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/ADAM S BOWEN/Examiner, Art Unit 2897
Prosecution Insights