DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on July 15, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
The information disclosure statement (IDS) submitted on May 9, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to because of the following reasons:
Regarding each of FIG. 3, FIG. 8, and FIG. 13: The connection of NVSS to the top NOR gate and then the line segment between the two NOR gats may cause confusion since the drawing does not even make it clear what node if any of the top NOR gate is being connected to the NVSS line. Examiner believes that Applicant intends to convey that a vertical line from NVSS 306 node runs vertically through the top NOR gate, then connects to a ground input terminal of the top NOR gate, then runs through the lower NOR gate and connects to a ground input terminal of the lower NOR gate. This should be drawn better in the figure and/or be stated in the specification.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
There are errors in the specification. Examiner is not afforded time to identify and correct all errors in Applicant’s disclosure so it is requested of Applicant to review the specification and correct any determined errors.
For example, it is suggested to amend paragraph [0028] as follows:
[0028] FIG. 2 is a detailed diagram of a proposed memory architecture in an [[a]] SRAM , in accordance with embodiments. The memory architecture may include a latch 204, a clock generator 201, a data latch 107, a control circuit 106, write drivers 102, 112, and memory arrays 110, 113 . In one embodiment, the control circuit 106 is configured to receive a clock signal 202 from the clock generator 201, an address signal 203 from the latch 204, and to generate a negative bit line input signal NBL 104 and write signals 105 . The clock signal 202 is utilized for timing coordination within the control circuit 106, and the address signal 203 from the latch 204 is used to determine the location in the memory cell at which the data will be written. A write decoder 205 within the control circuit 106 may be configured to decode the address signal 203 and generate one or more write signals 105. In one example, one write signal WRITEB_T 105 is enabled for accessing a top memory array 110, and another write signal WRITEB_B 111 is enabled for accessing a bottom memory array 113. Each write driver102,105 may be configured to receive a negative bit line input signal NBL 104, a write signal 105 and a data signal LDATA 103 from the data latch 107 and to generate a negative bit line voltage to one of two bit lines (108, 109) of a corresponding memory array (110, 113). The data signal LDATA 103 from the data latch 107 may determine the data (i.e., a “0” or a “1”) that will be written to the memory cell. The write driver 102 includes a voltage limiter circuit 101 that may be configured to control a voltage at a first node of a negative bit line (108, 109). For example, the voltage limiter circuit 101 may be configured to limit a magnitude of the negative bit line voltage on one of the two bit lines (108, 109) of the memory cell such that the magnitude does not exceed a predefined threshold.
The rest of the specification should be reviewed and corrected, if necessary, in a similar manner.
Appropriate correction is required.
Claim Objections
Claim 4 is objected to because of the following informalities:
Regarding claim 4: To correct the typographical error, it is suggested to amend the claim as follows:
The write driver of claim 1, wherein the voltage limiter circuit is further configured to reduce an active power of an SRAM cell at a high operating voltage mode .
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,073,877 (hereinafter “reference patent”). Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reasons.
Regarding claims 1 and 2: Claim 1 of the reference patent teaches this subject matter.
Regarding claim 3: Claim 2 of the reference patent teaches this subject matter.
Regarding claim 4: Claim 3 of the reference patent teaches this subject matter.
Regarding claim 5: Claim 4 of the reference patent teaches this subject matter.
Regarding claim 6: Claim 5 of the reference patent teaches this subject matter.
Regarding claim 11: Claim 11 of the reference patent teaches this subject matter.
Regarding claim 12: Claim 12 of the reference patent teaches this subject matter.
Regarding claim 13: Claim 13 of the reference patent teaches this subject matter.
Regarding claim 14: Claim 14 of the reference patent teaches this subject matter.
Regarding claims 15-20: Claims 15-20, respectively, teach the subject matter of these claims.
Regarding claim 1: Claim 15 of the reference patent teaches a write driver configured to generate a negative bit line voltage to one of two bit lines of a memory cell (see the claim element beginning with “a write driver”), the write driver comprising:
a voltage limiter circuit configured to control a voltage at a first node, the voltage limiter circuit being configured to limit a magnitude of the negative bit line voltage on said one of the two bit lines of the memory cell (see “a voltage limiter circuit configured to limit a magnitude of the negative bit line voltage on said one of the two bit liens of the memory cell”).
Regarding claims 9-10: Claims 19-20 of the reference patent teach the subject matter of these claims.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 8 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 8: The claim refers to “the active low negative bit line” but there is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 and 7-8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wu et al. (US 2015/0131366 A1; hereinafter “Wu”).
Regarding claim 1: Wu (FIG. 1, FIG. 3, FIG. 4, and FIG. 5) teaches a write driver (104, 106, and 108 of FIG. 1 that comprises the circuit in FIG. 3) configured to generate a negative bit line voltage to one of two bit lines of a memory cell (one of the two lines to SRAM cell 102 in FIG. 1), the write driver comprising:
a voltage limiter circuit (Voltage Controller 302 in FIG. 3, details of which are illustrated in FIG. 4) configured to control a voltage at a first node (234 or 220), the voltage limiter circuit being configured to limit a magnitude of the negative bit line voltage on said one of the two bit lines of the memory cell (302 limits the magnitude of the negative voltage on node 220, which is illustrated as signal 510 in FIG. 5; see [0015, 0023, 0025, 0026,0029]).
Regarding claim 2: The write driver of claim 1, wherein the writer drive further comprises a capacitor (transistor 222 in FIG. 3 is recognized by one of ordinary skill in the art to be configured as a capacitor since one S/D terminal is shorted to the other forming a capacitor plate while the gate of the transistor is another capacitor plate; such a transistor is inherently a two plate capacitor) responsive to the first node (a first plate of the capacitor is connected to the node 234) and configured to provide a transition of the negative bit line voltage over a period of time (the second plate of the capacitor is connected to node 220 that has its voltages transition to a negative voltage that is provided to a bit line of the SRAM cell 102 in FIG. 1; see signal 510 in FIG. 5).
Regarding claim 3: Wu teaches the write driver of claim 1, wherein the voltage limiter circuit is further configured to limit the magnitude of the negative bit line voltage while permitting the negative bit line voltage to reach a write operation threshold level (see [0015, 0023, 0025, 0026, 0029]; the magnitude of the negative boost voltage is limited to an amount or by an amount sufficient to perform a write operation or write cycle; FIG. 5).
Regarding claim 4: Wu teaches The write driver of claim 1, wherein the voltage limiter circuit is further configured to reduce an active power of an SRAM cell at a high operating voltage mode (a time “when the first source voltage increases” as stated in [0015] and other paragraphs; active power is reduced since a voltage is now provided that is “less than a voltage believed to damage components” as stated in [0015]); also see [0012]; a lower voltage magnitude is used; hence, active power is reduced).
Regarding claim 7: Wu ([0019]; FIG. 4) teaches the write driver of claim 1, wherein the voltage limiter circuit comprises a diode circuit (transistor 412 in FIG. 4 is configured as a diode since its gate is shorted to one of its source/drain terminals) configured to clamp the first node (234 or 220 via the diode) at a predefined voltage level ([0015, 0023-0025]).
Regarding claim 8: In so far as definite, Wu teaches the write driver of claim 7, wherein the diode circuit comprises a transistor (transistor 412 in FIG. 4), and wherein:
[a] source terminal of the transistor is coupled to a supply voltage node (see upper diffusion terminal connected to first voltage source 402);
drain terminal of the transistor is coupled to [the active low negative bit line] (node 234); and
the active low negative bit line (234) is coupled to the first node (to the first node 220 via the transistor 222, which is configured as a capacitor).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
Claim(s) 6, and 11-16 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2015/0131366 A1; hereinafter “Wu”) in view of Jandardan et al. (US 2012/0170391 A1).
Regarding claim 6: Wu does not specifically teach the write driver of claim 4, wherein each of the two bit lines further comprise [comprises] a pass gate MOSFET configured to transfer one or more write operation data signals from the write driver to the memory array.
Janardan (FIG. 1B; [0081-0086]) teaches applying a negative bit line voltage to a memory cell via bit line select transistors seen in circuit 5 of FIG. 1B controlled by NOR gates, wherein the negative bit line voltage (see “negative boost” or “negative bump” in [0005-0007, 0078-0084]) on node 8 is transferred to one of the bit lines during the writing of data to the memory cell, and is therefore considered to be a write operation data signal. Each NOR gate receives a write enable signal and one of a data or data compliment signal such that one of the bit lines of the complementary bit line pair is driven by or coupled to a negative boost voltage generated on node 8 of FIG.1 B.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Janardan into the device and/or method of Wu in a manner such that the negative bit line voltage on node 220 in FIG. 3 of Wu would be transferred to one of two bit lines of the memory cell 102 in FIG. 1 as a write operation data signal via a bit line select transistor based on a datum and/or datum complement signal, wherein each bit line of the SRAM cell comprises or is connected to such a bit line select transistor that is selected or deselected based on the datum or datum complement (one of the pair of select transistors is selected per column of an array based on the datum to be written to the memory cell of that column) by using NOR gates like that taught by Janardan. Hence, the write driver would further comprise bit line select transistors, each controlled by a respective NOR gate, and this circuit would provide more detail of the MUX 104 in FIG. 1 of Wu. The motivation to provide further detail of the circuitry of the MUX 104 in FIG. 1 of Wu to apply the negative boost voltage to one of the bit lines in a write cycle by selecting one of the bit lines based on write data (data to be written in the write operation or write cycle) as was already exemplified by Janardan to be a suitable way of selecting one bit line of a pair of bit lines to transfer a negative voltage to during such an operation in an SRAM, which is typically referred to as a write-assist operation (see “write assist operation” in [0007] of Janardan).
Regarding claim 11: Wu (FIG. 1, FIG. 3, FIG. 4, and FIG. 5) teaches a method of operating a write driver, comprising:
generating a negative bit line voltage (see negative voltage of node 220 represented by signal 510 in FIG. 5), wherein a magnitude of the negative bit line voltage is limited to not exceed a predetermined value (as is explained in [0015, 0023, 0025, 0026,0029]).
Wu does not specifically teach applying the negative bit line voltage to one of two bit lines based on a data signal.
Janardan (FIG. 1B; [0081-0086]) teaches applying a negative bit line voltage to a memory cell via bit line select transistors seen in circuit 5 of FIG. 1B controlled by NOR gates, wherein the negative bit line voltage (see “negative boost” or “negative bump” in [0005-0007, 0078-0084]) on node 8 is transferred to one of the bit lines during the writing of data to the memory cell, and is therefore considered to be a write operation data signal. Each NOR gate receives a write enable signal and one of a data or data compliment signal such that one of the bit lines of the complementary bit line pair is driven by or coupled to a negative boost voltage generated on node 8 of FIG.1 B.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Janardan into the device and/or method of Wu in a manner such that the negative bit line voltage on node 220 in FIG. 3 of Wu would be transferred to one of two bit lines of the memory cell 102 in FIG. 1 as a write operation data signal via a bit line select transistor based on a datum (data signal) and/or datum complement signal, wherein each bit line of the SRAM cell comprises or is connected to such a bit line select transistor that is selected or deselected based on the datum or datum complement (one of the pair of select transistors is selected per column of an array based on the datum to be written to the memory cell of that column) by using NOR gates like that taught by Janardan. Hence, the write driver would further comprise bit line select transistors, each controlled by a respective NOR gate, and this circuit would provide more detail of the MUX 104 in FIG. 1 of Wu. The motivation to provide further detail of the circuitry of the MUX 104 in FIG. 1 of Wu to apply the negative boost voltage to one of the bit lines in a write cycle by selecting one of the bit lines based on write data (data to be written in the write operation or write cycle) as was already exemplified by Janardan to be a suitable way of selecting one bit line of a pair of bit lines to transfer a negative voltage to during such an operation in an SRAM, which is typically referred to as a write-assist operation (see “write assist operation” in [0007] of Janardan).
Regarding claim 12: Wu as modified above teaches the method of claim 11, wherein the step of limiting the magnitude of the negative bit line voltage is accomplished during a high operating voltage mode of a SRAM cell (at a time “when the first source voltage increases” as is disclosed in [0015] of Wu).
Regarding claim 13: Wu as modified above teaches the method of claim 11, further comprising determining the magnitude of the negative bit line voltage (a magnitude seen in FIG. 5) necessary for performing a successful write operation (Wu inherently teaches this subject matter since a specified voltage threshold of a fifth voltage peak level is known and avoided or inhibited as disclosed in [0015], for example, by limiting the value of signal 510 to a value that is still sufficient to. Perform a successful write operation as illustrated in FIG. 5).
Regarding claim 14: Wu teaches the method reduces an active power of an SRAM cell (at a time “when the first source voltage increases” as stated in [0015] and other paragraphs; active power is reduced since a voltage is now provided that is “less than a voltage believed to damage components” as stated in [0015]); also see [0012]; a lower voltage magnitude is used; hence, active power is reduced).
Regarding claim 15: Wu (FIG. 1, FIG. 3, FIG. 4, and FIG. 5) teaches a memory circuit, comprising:
a memory (100 in FIG. 1) comprising an SRAM cell (102), the memory being configured to receive one or more write operation data signals (data is written to SRAM cell 102, see [0009]. Also, any of the signals in or input to FIG. 3 may be referred to as write operation data signals) and to perform a write operation to a memory location (see “write cycle” in [0009, 0011, 0014, 0024]); and
a write driver (FIG. 3) configured to generate the one or more write operation data signals including a negative bit line voltage to one of two bit lines of a particular memory cell (a negative boost voltage on 220 is applied to the SRAM cell via one of the two lines connected to the SRAM cell 102 seen in FIG. 1; see signal 510 in FIG. 5), the write driver comprising a voltage limiter circuit (voltage controller 302 or diode transistor 412 in voltage controller 302 as seen in FIG. 4) configured to limit a magnitude of the negative bit line voltage on said one of the two bit lines of the memory cell (by limiting the magnitude of the negative voltage on node 220; see [0015, 0023, 0025, 0026,0029]; see FIG. 5).
Wu does not specifically teach a memory array including a plurality of transistors and a plurality of bit lines that form a plurality of memory cells, the memory array being configured to receive one or more write operation data signals and to perform a write operation to a memory location.
Janardan ([0003]) teaches an SRAM memory array including a plurality of transistors and a plurality of bit lines that form a plurality of memory cells, and Janardan (FIG. 1B; [0081-0086]) teaches applying a negative bit line voltage to a memory cell via bit line select transistors seen in circuit 5 of FIG. 1B controlled by NOR gates, wherein the negative bit line voltage (see “negative boost” or “negative bump” in [0005-0007, 0078-0084]) on node 8 is transferred to one of the bit lines during the writing of data to the memory cell, and is therefore considered to be a write operation data signal. Each NOR gate receives a write enable signal and one of a data or data compliment signal such that one of the bit lines of the complementary bit line pair is driven by or coupled to a negative boost voltage generated on node 8 of FIG.1 B.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Janardan into the device and/or method of Wu in a manner such that the memory cell 102 would be part of an array of memory cells like that taught by Janardan, and the negative bit line voltage on node 220 in FIG. 3 of Wu would be transferred to one of two bit lines of the memory cell 102 in FIG. 1 as a write operation data signal via a bit line select transistor based on a datum and/or datum complement signal, wherein each bit line of the SRAM cell comprises or is connected to such a bit line select transistor that is selected or deselected based on the datum or datum complement (one of the pair of select transistors is selected per column of an array based on the datum to be written to the memory cell of that column) by using NOR gates like that taught by Janardan. Hence, the write driver would further comprise bit line select transistors, each controlled by a respective NOR gate, and this circuit would provide more detail of the MUX 104 in FIG. 1 of Wu. The motivation to provide further detail of the circuitry of the MUX 104 in FIG. 1 of Wu to apply the negative boost voltage to one of the bit lines in a write cycle by selecting one of the bit lines based on write data (data to be written in the write operation or write cycle) as was already exemplified by Janardan to be a suitable way of selecting one bit line of a pair of bit lines to transfer a negative voltage to during such an operation in an SRAM, which is typically referred to as a write-assist operation (see “write assist operation” in [0007] of Janardan).
Regarding claim 16: Wu as modified above teaches the memory circuit of claim 15, wherein each of the one or more bit lines further comprise a pass gate MOSFET (see bit line select transistors from circuit 5 in FIG. 1B of Janardan) configured to transfer the one or more write operation data signals from a write driver to the memory array.
Regarding claim 18: Wu ([0019]; FIG. 4) as modified teaches the memory circuit of claim 15, the voltage limiter circuit comprising a diode circuit (transistor 412 in FIG. 4 is configured as a diode since its gate is shorted to one of its source/drain terminals) configured to clamp a node of an active low negative bit line at a predefined voltage level such as to limit the magnitude of negative voltage that is coupled to the one of the two bit lines to not exceed a predefined threshold ([0015, 0023-0025]).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2015/0131366 A1; hereinafter “Wu”) in view of Janardan et al. (US 2013/0170391 A1; hereinafter “Janardan”) and Pawlowski (US 2002/0009014 A1).
Regarding claim 5: Wu teaches the write driver of claim 1, the write driver being coupled to:
a memory cell (102 in FIG. 1) configured to receive the negative bit line voltage and to perform a write operation to the memory cell, the memory cell connected to the two bit lines (the two lines connected to 102 in FIG. 1); and
a control circuit (108 in FIG. 1 or 300 in FIG. 3) configured to generate a negative bit line input signal (SIGNAL 2 on node 234) and a write signal (SIGNAL1 or SIGNAL6).
Wu does not specifically teach:
a memory array configured to receive the negative bit line voltage and to perform the write operation to the memory cell, the memory array including one or more transistors and the two bit lines, and a data signal.
Janardan ([0003]) teaches an SRAM memory array including a plurality of transistors and a plurality of bit lines that form a plurality of memory cells, and Janardan (FIG. 1B; [0081-0086]) teaches applying a negative bit line voltage to a memory cell via bit line select transistors seen in circuit 5 of FIG. 1B controlled by NOR gates, wherein the negative bit line voltage (see “negative boost” or “negative bump” in [0005-0007, 0078-0084]) on node 8 is transferred to one of the bit lines during the writing of data to the memory cell, and is therefore considered to be a write operation data signal. Each NOR gate receives a write enable signal and one of a data or data compliment signal such that one of the bit lines of the complementary bit line pair is driven by or coupled to a negative boost voltage generated on node 8 of FIG.1 B.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Janardan into the device and/or method of Wu in a manner such that the memory cell 102 would be part of an array of memory cells like that taught by Janardan, and the negative bit line voltage on node 220 in FIG. 3 of Wu would be transferred to one of two bit lines of the memory cell 102 in FIG. 1 as a write operation data signal via a bit line select transistor based on a datum and/or datum complement signal (each of which may be called a data signal), wherein each bit line of the SRAM cell comprises or is connected to such a bit line select transistor that is selected or deselected based on the datum or datum complement (one of the pair of select transistors is selected per column of an array based on the datum to be written to the memory cell of that column) by using NOR gates like that taught by Janardan. Hence, the write driver would further comprise bit line select transistors, each controlled by a respective NOR gate, and this circuit would provide more detail of the MUX 104 in FIG. 1 of Wu. The motivation to provide further detail of the circuitry of the MUX 104 in FIG. 1 of Wu to apply the negative boost voltage to one of the bit lines in a write cycle by selecting one of the bit lines based on write data (data to be written in the write operation or write cycle) as was already exemplified by Janardan to be a suitable way of selecting one bit line of a pair of bit lines to transfer a negative voltage to during such an operation in an SRAM, which is typically referred to as a write-assist operation (see “write assist operation” in [0007] of Janardan).
Wu as modified above does not specifically teach a data latch configured to generate the data signal.
Pawlowski states in [0006] “In pipelined memory devices, data is typically read from a memory array during one clock cycle and provided on the data bus during the next clock cycle, Similarly, data to be written to a memory array is typically latched from the data bus during one clock cycle and written to the memory array during the next clock cycle.”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Pawlowski into the device and/or method of Wu as modified above in a manner such that a data latch would be configured to generate at least one of the two data signals, the datum and its complement per each column of the array in response to a clock. The motivation to do so would have been to implement a typical pipelined memory as disclosed by Pawlowski.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2015/0131366 A1; hereinafter “Wu”) as modified by Janardan et al. (US 2013/0170391 A1; hereinafter “Janardan”) in view of Manapat et al. (US 6,327,175).
Regarding claim 17: Wu teaches the memory circuit further comprising:
a control circuit (circuitry of an SRAM comprising 104, 106, and 108 of FIG. 1, which further comprises 300 in FIG. 3) configured to generate a negative bit line input signal (SIGNAL 2 on node 234) and a write signal (SIGNAL1 or SIGNAL6).
Wu does not specifically teach:
the control circuit configured to receive a clock signal and an address signal; and
the memory circuit further comprising a data latch configured to generate a data signal.
Manapat (FIGURE 1; columns 1 and 2) teaches a conventional SRAM memory device comprising:
control circuitry (clock input circuit 26 of FIGURE 1) configured to receive a clock signal (Clk 28) and control circuitry (ADDRESS REGISTERS 14) configured to receive an address signal (signal on ADDRESS BUS 12); and
a data latch (DATA REGISTERS 18) configured to generate a data signal (data signals 38).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Manapat into the device and/or method of Wu as modified above in a manner such that the device would would further comprise circuitry like that taught by Manapat that would be configured to receive a clock signal and an address signal; and
the device would further comprise a data latch like the data register of Manapat that would be configured to generate the data signal from Janardan.
Note that each of the circuits may be included in the memory device and/or in the same control circuit that comprises the write driver and provide input to the write driver consistent with what is taught by Wu to realize the write cycle operation disclosed by Wu. The motivation to do so would have been to provide peripheral circuitry for controlling the memory that is already known to be used in conventional memory devices as exemplified by Manapat and suitable for controlling an SRAM type memory.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY W RADKE whose telephone number is (571)270-1622. The examiner can normally be reached M-F 9-6 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JAY W. RADKE
Primary Examiner
Art Unit 2827
/JAY W. RADKE/Primary Examiner, Art Unit 2827
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