Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. US 12,068,363 B2 to Cheng et al.
Although the claims at issue are not identical, they are not patentably distinct from each other because the Parent Patent renders obvious the Instant Application.
Regarding independent claim 1: Cheng teaches (e.g., Claims 1-7) a semiconductor device, comprising:
one or more low dielectric constant (low-κ) layers on a substrate;
a dielectric layer on the one or more low-κ layers, wherein an opening resides within the substrate, the one or more low-κ layers, and the dielectric layer;
a capping layer directly on opposing sides of a portion of the opening that intersects with the one or more low-κ layers and the dielectric layer; and
a structure in the opening and between the capping layer and the substrate (Claim 1).
Regarding claim 2: Cheng teaches the claim limitation of the semiconductor device of claim 1, on which this claim depends,
wherein the one or more low-κ layers comprises a plurality of low-κ layers (Claim 1).
Regarding claim 3: Cheng teaches the claim limitation of the semiconductor device of claim 1, on which this claim depends,
wherein the capping layer resides on a portion of a top surface of the substrate (Claim 1).
Regarding claim 4: Cheng teaches the claim limitation of the semiconductor device of claim 1, on which this claim depends,
wherein the capping layer comprises at least one of silicon nitride, silicon carbonitride, silicon carbide, or amorphous silicon (Claim 6).
Regarding claim 5: Cheng teaches the claim limitation of the semiconductor device of claim 1, on which this claim depends,
wherein a thickness of the capping layer is in a range from approximately 50 angstroms (Å) to approximately 1000 Å (Claim 4).
Regarding claim 6: Cheng teaches the claim limitation of the semiconductor device of claim 1, on which this claim depends,
further comprising: a liner layer directly on the capping layer and the substrate, wherein the structure is within and directly on the liner layer (Claim 5).
Regarding claim 7: Cheng teaches the claim limitation of the semiconductor device of claim 6, on which this claim depends,
wherein a thickness of the capping layer is approximately 10% to approximately 100% of a thickness of the liner layer (Claim 5).
Regarding independent claim 8: Cheng teaches (e.g., Claims 9-12 and 14-17) a method, comprising:
depositing a capping layer in one or more openings and on a dielectric layer and one or more low dielectric constant (low-κ) layers,
wherein the dielectric layer resides on the one or more low-κ layers, and wherein the one or more low-κ layers reside on a substrate;
depositing a liner layer in the opening and directly on the capping layer and the substrate; and
forming a structure in the opening and directly on the liner layer (Claim 1).
Regarding claim 9: Cheng teaches the claim limitation of the method of claim 8, on which this claim depends,
wherein the capping layer is formed in a first opening of the one or more openings, wherein the first opening is through the dielectric layer and the one or more low-κ layers (Claim 10).
Regarding claim 10: Cheng teaches the claim limitation of the method of claim 9, on which this claim depends,
wherein a bottom of the first opening intersects with a portion of a top of the substrate (Claim 11).
Regarding claim 11: Cheng teaches the claim limitation of the method of claim 10, on which this claim depends,
wherein depositing the capping layer in the one or more openings and on the dielectric layer and the one or more low-κ layers comprises:
forming the first opening through the dielectric layer and the one or more low-κ layers;
depositing the capping layer in the opening and directly on sides of the dielectric layer and the one or more low-κ layers and on the portion of the top of the substrate; and
forming a second opening through the top of the substrate (Claim 12).
Regarding claim 12: Cheng teaches the claim limitation of Cheng teaches the claim limitation of the method of claim 8, on which this claim depends, further comprising:
depositing a barrier layer on the liner layer, wherein the structure is formed within the barrier layer (Claim 12).
Regarding claim 14: Cheng teaches the claim limitation of the method of claim 8, on which this claim depends,
wherein the one or more low-κ layers comprises a plurality of low-κ layers (Claim 10).
Regarding claim 15: Cheng teaches the claim limitation of the method of claim 8, on which this claim depends,
wherein a thickness of the capping layer varies along a depth of the one or more openings (Claim 15).
Regarding claim 16: Cheng teaches the claim limitation of the method of claim 8, on which this claim depends,
wherein a thickness of the liner layer varies along a depth of the one or more openings (Claim 14).
Regarding independent claim 17: Cheng teaches (e.g., Claims 18-20) a method, comprising:
depositing a capping layer on sidewalls of an opening such that the capping layer is directly deposited on at least exposed surfaces of one or more low dielectric constant (low-κ) layers on a substrate; and
depositing a liner layer directly on the capping layer and within the opening (Claim 18).
Regarding claim 18: Cheng teaches the claim limitation of the method of claim 17, on which this claim depends,
wherein the one or more low-κ layers comprises a plurality of low-κ layers (Claim 18).
Regarding claim 19: Cheng teaches the claim limitation of the method of claim 18, on which this claim depends,
comprising: forming, after depositing the capping layer on the sidewalls of the opening, a second opening through the substrate, wherein the liner layer is further deposited directly on the substrate.
Regarding independent claim 17: Cheng teaches (e.g., Claims 9-17) a method, comprising:
depositing a capping layer on sidewalls of an opening such that the capping layer is directly deposited on at least exposed surfaces of one or more low dielectric constant (low-κ) layers on a substrate; and
depositing a liner layer directly on the capping layer and within the opening (Claim 9).
Regarding claim 20: Cheng teaches the claim limitation of the method of claim method of claim 18, on which this claim depends,
comprising: forming a through-silicon via (TSV) or a deep trench capacitor (DTC) in the opening (Claim 12).
Claim 13 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim (e.g., Claims 9-12 and 14-17) of U.S. Patent No. US 12,068,363 B2 to Cheng et al. in view of Patent No. US 2015/0028494 A1 to Park et al.
Regarding claim 13: Cheng teaches the claim limitation of the method of claim 12, on which this claim depends,
Cheng does not expressly teach that the method further comprises
depositing a seed layer on the barrier layer, wherein the structure is formed within the seed layer.
Park teaches (e.g., Fig. 4; using Fig. 1 for element designation purposes, see [0084]) a method comprising
depositing a seed layer ([0153]) on a barrier layer ([0153]: 162), wherein a structure ([0062]: 32) is formed within the seed layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the method of Cheng, the method of depositing a seed layer on the barrier layer, wherein the structure is formed within the seed layer, as taught by Park, for the benefits of improving the quality of the deposition process of the subsequent structure, thus improving the contact resistance of the interconnection; which in turn, improves the device signal speed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 8-10 and 17-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Han et al. (US 2015/0155233 A1).
Regarding independent claim 1: Han teaches (e.g., Figs. 1A-1H) a semiconductor device, comprising:
one or more low dielectric constant (low-κ) layers ([0043]-[0044]: first low dielectric constant (low-κ) layer 123 and second low dielectric constant (low-κ) layer 123 from bottommost layer of 120) on a substrate ([0042]: 100);
a dielectric layer ([0042]: 130) on the one or more low-κ layers,
wherein an opening ([0047]: 101) resides within the substrate, the one or more low-κ layers (123 and 123), and the dielectric layer (130);
a capping layer ([0054] and [0059]-[0060]: 140) directly on opposing sides of a portion of the opening that intersects with the one or more low-κ layers and the dielectric layer; and
a structure ([0060] and [0063]-[0065]: 155) in the opening (101) and between the capping layer and the substrate (100).
Regarding claim 2: Han teaches the claim limitation of the semiconductor device of claim 1, on which this claim depends,
wherein the one or more low-κ layers comprises a plurality of low-κ layers ([0043]-[0044]: first low dielectric constant (low-κ) layer 123 and second low dielectric constant (low-κ) layer 123 from bottommost layer of 120).
Regarding independent claim 8: Han teaches (e.g., Figs. 1A-1H) a method, comprising:
depositing a capping layer ([0054] and [0059]-[0060]: 140) in one or more openings ([0047]: 101) and on a dielectric layer ([0042]: 130) and one or more low dielectric constant (low-κ) layers ([0043]-[0044]: first low dielectric constant (low-κ) layer 123 and second low dielectric constant (low-κ) layer 123 from bottommost layer of 120),
wherein the dielectric layer (130) resides on the one or more low-κ layers (123 and 123), and
wherein the one or more low-κ layers reside on a substrate ([0042]: 100);
depositing a liner layer (Fig. 1E; [0059]: 151) in the opening and directly on the capping layer (140) and the substrate (100); and
forming a structure ([0062] and [0064]-[0065]: 155) in the opening and directly on the liner layer (151).
Regarding claim 9: Han teaches the claim limitation of the method of claim 8, on which this claim depends,
wherein the capping layer is formed in a first opening ([0047]: 101) of the one or more openings, wherein the first opening is through the dielectric layer (130) and the one or more low-κ layers (123).
Regarding claim 10: Cheng teaches the claim limitation of the method of claim 9, on which this claim depends,
wherein a bottom of the first opening intersects with a portion of a top of the substrate (100).
Regarding independent claim 17: Han teaches (e.g., Figs. 1A-1H) a method, comprising:
depositing a capping layer ([0054] and [0059]-[0060]: 140) on sidewalls of an opening ([0047]: 101) such that the capping layer (140) is directly deposited on at least exposed surfaces of one or more low dielectric constant (low-κ) layers ([0043]-[0044]: first low dielectric constant (low-κ) layer 123 and second low dielectric constant (low-κ) layer 123 from bottommost layer of 120) on a substrate ([0042]: 100); and
depositing a liner layer (Fig. 1E; [0059]: 151) directly on the capping layer (140) and within the opening (101).
Regarding claim 18: Han teaches the claim limitation of the method of claim 17, on which this claim depends,
wherein the one or more low-κ layers comprises a plurality of low-κ layers ([0043]-[0044]: first low dielectric constant (low-κ) layer 123 and second low dielectric constant (low-κ) layer 123 from bottommost layer of 120).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (US 2015/0155233 A1) in view of Tsao et al. (US 2012/0142190 A1).
Regarding claim 3: Han teaches the claim limitation of the semiconductor device of claim 1, on which this claim depends,
Han does not expressly teach that the capping layer resides on a portion of a top surface of the substrate.
Tsao teaches (e.g., 2A-2G) a semiconductor device comprising a capping layer ([0024]: layer 218 caps the surface of the substrate 202; thus, it is considered a capping layer) residing on a portion of a top surface of a substrate (202).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the device of Cheng, the capping layer that resides on a portion of a top surface of the substrate, as taught by Tsao, for the benefits of isolating the inner structure from the substrate and reducing the possibility of metal diffusion and contamination into the adjacent active devices.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (US 2015/0155233 A1) in view of Park et al. (US 2015/0028494 A1).
Regarding claim 4: Han teaches the claim limitation of the semiconductor device of claim 1, on which this claim depends,
Han does not expressly teach that the capping layer comprises at least one of silicon nitride, silicon carbonitride, silicon carbide, or amorphous silicon.
Park teaches (e.g., Fig. 4; [0084]: In FIG. 4, the same elements as those in FIG. 1A are denoted by the same reference numerals, and a detailed explanation thereof will not be given) a semiconductor device, comprising:
a capping layer ([0066]: 40; [0084];” FIG. 4 is a cross-sectional view illustrating an integrated circuit device 10D according to another embodiment of the inventive concept. In FIG. 4, the same elements as those in FIG. 1A are denoted by the same reference numerals, and a detailed explanation thereof will not be given”).
Park further teaches that the capping layer comprises at least one of silicon nitride, silicon carbonitride, silicon carbide, or amorphous silicon ([0053], [0066] and [0084]: silicon nitride; see [0133]).
It is noted that silicon nitride is known as a suitable material for a capping layer.
Applicant is reminded that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) (Claims to a printing ink comprising a solvent having the vapor pressure characteristics of butyl carbitol so that the ink would not dry at room temperature but would dry quickly upon heating were held invalid over a reference teaching a printing ink made with a different solvent that was nonvolatile at room temperature but highly volatile when heated in view of an article which taught the desired boiling point and vapor pressure characteristics of a solvent for printing inks and a catalog teaching the boiling point and vapor pressure characteristics of butyl carbitol.
"Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.) MPEP 2144.07.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the device of Han, the capping layer comprising at least a silicon nitride, as taught by Park, since silicon nitride is known to be a suitable material for insulating adjacent layers, and thus, improving the protection around the via structure.
Allowable Subject Matter
Claims 5-7,11-16, 19-20 are objected to as being dependent upon rejected base claims, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and after overcoming all the rejections made of record above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HERVE-LOUIS Y ASSOUMAN whose telephone number is (571)272-2606. The examiner can normally be reached M-F: 08:30 AM-5:30 PM.
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/HERVE-LOUIS Y ASSOUMAN/ Examiner, Art Unit 2812
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