DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/15/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 20 is objected to because of the following informalities:
In claim 20, line 2, the limitation of “first and second semiconductor layers” should be corrected into “first and second nanostructured layers”. Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1, 3-4, 7 and 9-10 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2 and 8-9 of U.S. Patent No. 11,594,638. Although the claims at issue are not identical, they are not patentably distinct from each other because the conflicting claims have been patented.
Regarding claim 1, Pat '638 discloses, in claim 1, a semiconductor device, comprising:
a substrate; a plurality of nanostructures disposed on the substrate; a gate structure disposed on the plurality of nanostructures; a source/drain region, comprising: a first source/drain portion and a second source/drain portion in contact with the first source/drain portion; and a dielectric layer disposed on one of the nanostructures of the plurality of nanostructures and in contact with the first source/drain portion ("a plurality of nanostructures on a substrate; a source/drain region in contact with the plurality of nanostructures, comprising: a plurality of epitaxial end caps, wherein each epitaxial end cap is formed at an end portion of a nanostructure of the plurality of nanostructures; an epitaxial body in contact with the plurality of epitaxial end caps; and an epitaxial top cap formed on the epitaxial body; a gate structure formed on the plurality of nanostructures; and a dielectric layer disposed on one of the nanostructures of the plurality of nanostructures and in contact with one of the epitaxial end caps of the plurality of epitaxial end caps", in claim 1 of Pat '638, is interpreted as the same limitation).
Pat '638 does not explicitly disclose a first source/drain portion comprising a dopant, and a second source/drain portion comprising the dopant and in contact with the first source/drain portion, wherein a concentration of the dopant in the first source/drain portion is different from a concentration of the dopant in the second source/drain portion.
Pat '638 teaches, in claim 11, a first source/drain portion comprising a dopant, and a second source/drain portion comprising the dopant and in contact with the first source/drain portion, wherein a concentration of the dopant in the first source/drain portion is different from a concentration of the dopant in the second source/drain portion ("a plurality of epitaxial end caps, wherein an epitaxial end cap is formed at an end portion of the nanostructure and comprises a first dopant concentration; an epitaxial body in contact with the epitaxial end cap and comprising a second dopant concentration greater than the first dopant concentration", in claim 11 of Pat '638, is interpreted as the same limitation), for the purpose of providing multi-step epitaxial source/drain structures to improve device performance, reliability, and yield.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in claim 1 of Pat '638 to have the first source/drain portion comprising a dopant, and the second source/drain portion comprising the dopant and in contact with the first source/drain portion, wherein a concentration of the dopant in the first source/drain portion is different from a concentration of the dopant in the second source/drain portion, as taught by claim 11 of Pat '638, for the purpose of providing multi-step epitaxial source/drain structures to improve device performance, reliability, and yield. as described above.
Regarding claim 3, Pat '638 discloses the semiconductor device of claim 1 as described above.
Pat '638 further discloses, in claim 2, the first source/drain portion comprises curved sidewall profiles ("each epitaxial end cap of the plurality of epitaxial end caps comprises a crescent cross-sectional shape", in claim 2 of Pat '638, is interpreted as the same limitation).
Regarding claim 4, Pat '638 discloses the semiconductor device of claim 1 as described above.
Pat '638 further discloses, in claim 2, the first source/drain portion comprises a crescent-shaped cross-sectional profile ("each epitaxial end cap of the plurality of epitaxial end caps comprises a crescent cross-sectional shape", in claim 2 of Pat '638, is interpreted as the same limitation).
Regarding claim 7, Pat '638 discloses the semiconductor device of claim 1 as described above.
Pat '638 further discloses, in claim 8, the first and second source/drain portions comprise materials different from each other ("the epitaxial body comprises a first atomic concentration of germanium and the plurality of epitaxial end caps comprises a second atomic concentration of germanium that is lower than the first atomic concentration of germanium", in claim 8 of Pat '638, is interpreted as the same limitation).
Regarding claim 9, Pat '638 discloses the semiconductor device of claim 1 as described above.
Pat '638 further discloses, in claim 1, a fourth source/drain portion disposed on the second source/drain portion ("an epitaxial top cap formed on the epitaxial body", in claim 1 of Pat '638, is interpreted as the same limitation).
Regarding claim 10, Pat '638 discloses the semiconductor device of claim 9 as described above.
Pat '638 further discloses, in claim 9, the second source/drain portion comprises a first concentration of germanium atoms, and wherein the fourth source/drain portion comprises a second concentration of germanium atoms that is greater than the first concentration of germanium atoms ("the epitaxial body comprises a first atomic concentration of germanium and the epitaxial top cap comprises a second atomic concentration of germanium that is greater than the first atomic concentration of germanium", in claim 9 of Pat '638, is interpreted as the same limitation).
Claims 2, 5-6 and 8 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 of U.S. Patent No. 11,594,638 in view of Wang (US 2021/0343639).
Regarding claim 2, Pat '638 discloses the semiconductor device of claim 1 as described above.
Pat '638 does not explicitly disclose the second source/drain portion is disposed on a sidewall of a spacer disposed on the gate structure.
Wang teaches, in at least figures 13A and related text, the device comprising the second source/drain portion (194, [58]) is disposed on a sidewall of a spacer (170, [48]) disposed on the gate structure (162, [45]), for the purpose of reducing the contact resistance between the backside via and the epitaxial regrowth layer([28]).
Pat '638 and Wang are analogous art because they are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '638 with the specified features of Wang because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '638 to have the second source/drain portion being disposed on a sidewall of a spacer disposed on the gate structure, as taught by Wang, for the purpose of reducing the contact resistance between the backside via and the epitaxial regrowth layer([28], Wang).
Regarding claim 5, Pat '638 discloses the semiconductor device of claim 1 as described above.
Pat '638 does not explicitly disclose the first source/drain portion is in contact with a sidewall of the dielectric layer.
Wang teaches, in at least figures 13A and related text, the device comprising the first source/drain portion (192, [58]) is in contact with a sidewall of the dielectric layer (162, [45]), for the purpose of reducing the contact resistance between the backside via and the epitaxial regrowth layer ([28]).
Pat '638 and Wang are analogous art because they are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '638 with the specified features of Wang because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '638 to have the first source/drain portion being in contact with a sidewall of the dielectric layer, as taught by Wang, for the purpose of reducing the contact resistance between the backside via and the epitaxial regrowth layer([28], Wang).
Regarding claim 6, Pat '638 discloses the semiconductor device of claim 1 as described above.
Pat '638 does not explicitly disclose a third source/drain portion disposed in the substrate and under the second source/drain portion, wherein the first and third source/drain portions comprise a same material.
Wang teaches, in at least figures 13A and related text, the device comprising a third source/drain portion (192, [58]) disposed in the substrate (112, [38]) and under the second source/drain portion (194, [58]), wherein the first (192, [58]) and third (192, [58]) source/drain portions comprise a same material, for the purpose of reducing the contact resistance between the backside via and the epitaxial regrowth layer ([28]).
Pat '638 and Wang are analogous art because they are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '638 with the specified features of Wang because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '638 to have the third source/drain portion disposed in the substrate and under the second source/drain portion, wherein the first and third source/drain portions comprise a same material, as taught by Wang, for the purpose of reducing the contact resistance between the backside via and the epitaxial regrowth layer([28], Wang).
Regarding claim 8, Pat '638 discloses the semiconductor device of claim 1 as described above.
Pat '638 does not explicitly disclose the second source/drain portion comprises a dopant concentration profile that decreases from a top surface of the second source/drain portion to a bottom surface of the second source/drain portion.
Wang teaches, in at least figures 13A and related text, the device comprising the second source/drain portion (194, [58]) comprises a dopant concentration profile that decreases from a top surface of the second source/drain portion to a bottom surface of the second source/drain portion ([58]), for the purpose of reducing the contact resistance between the backside via and the epitaxial regrowth layer ([28]).
Pat '638 and Wang are analogous art because they are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '638 with the specified features of Wang because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '638 to have the second source/drain portion comprising a dopant concentration profile that decreases from a top surface of the second source/drain portion to a bottom surface of the second source/drain portion, as taught by Wang, for the purpose of reducing the contact resistance between the backside via and the epitaxial regrowth layer([28], Wang).
Claims 11-13 and 15-16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 of U.S. Patent No. 11,594,638 in view of Lee (US 2021/0126135).
Regarding claim 11, Pat '638 discloses, in claim 1, a semiconductor device, comprising:
a substrate; a plurality of nanostructures disposed on the substrate; a source/drain region in contact with the plurality of nanostructures; a gate structure surrounding the plurality of nanostructures ("a plurality of nanostructures on a substrate; a source/drain region in contact with the plurality of nanostructures; a gate structure formed on the plurality of nanostructures", in claim 1 of Pat '638, is interpreted as the same limitation).
Pat '638 does not explicitly disclose a gate structure surrounding the plurality of nanostructures and comprising a gate spacer disposed on the nanostructures; a dielectric layer disposed between the gate spacer and one of the nanostructures of the plurality of nanostructures and in contact with the source/drain region.
Lee teaches, in at least figure 32B and related text, the device comprising a gate structure (170, [33]) surrounding the plurality of nanostructures (108, [12]) and comprising a gate spacer (131, [26]) disposed on the nanostructures (108, [12]); a dielectric layer (121, [22]) disposed between the gate spacer (131, [26]) and one of the nanostructures of the plurality of nanostructures (108, [12]) and in contact with the source/drain region (160, [45]), for the purpose of providing source/drain structure having the epitaxy structure for improving the device performance and reliability ([33]).
Pat '638 and Lee are analogous art because they are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '638 with the specified features of Lee because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '638 to have the gate structure surrounding the plurality of nanostructures and comprising a gate spacer disposed on the nanostructures; the dielectric layer disposed between the gate spacer and one of the nanostructures of the plurality of nanostructures and in contact with the source/drain region, as taught by Lee, for the purpose of providing source/drain structure having the epitaxy structure for improving the device performance and reliability ([33], Lee).
Regarding claim 12, Pat '638 in view of Lee discloses the semiconductor device of claim 11 as described above.
Lee further teaches, in at least figure 32B and related text, the source/drain region (160, [45]) comprises first (162 on 108, [45], figure), second (162 on 150, [45], figure), and third (164, [45]) regions, and wherein a portion of the third region (164, [45]) is disposed between the first (162 on 108, [45], figure) and second (162 on 150, [45], figure) regions, for the purpose of providing source/drain structure having the epitaxy structure for improving the device performance and reliability ([33]).
Regarding claim 13, Pat '638 in view of Lee discloses the semiconductor device of claim 12 as described above.
Lee further teaches, in at least figure 32B and related text, the second region (162 on 150, [45], figure) comprises top and bottom surfaces with curved profiles, for the purpose of providing source/drain structure having the epitaxy structure for improving the device performance and reliability ([33]).
Regarding claim 15, Pat '638 in view of Lee discloses the semiconductor device of claim 12 as described above.
Lee further teaches, in at least figure 32B and related text, the first region (162 on 108, [45], figure) and the plurality of nanostructures (108, [12]) comprise a same crystal orientation ([43]), for the purpose of providing source/drain structure having the epitaxy structure for improving the device performance and reliability ([33]).
Regarding claim 16, Pat '638 in view of Lee discloses the semiconductor device of claim 12 as described above.
Lee further teaches, in at least figure 32B and related text, the second region (162 on 150, [45], figure) and the substrate (100, [37]) comprise a same crystal orientation ([43]), for the purpose of providing source/drain structure having the epitaxy structure for improving the device performance and reliability ([33]).
Claim 14 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 of U.S. Patent No. 11,594,638 in view of Lee (US 2021/0126135), and further in view of claims 17 of U.S. Patent No. 12,170,335.
Regarding claim 14, Pat '638 in view of Lee discloses the semiconductor device of claim 12 as described above.
Pat '638 in view of Lee does not explicitly disclose the first region comprises a first crystal orientation, and wherein the second region comprises a second crystal orientation different from the first crystal orientation.
Pat ‘335 teaches, in claim 17, the first region comprises a first crystal orientation, and wherein the second region comprises a second crystal orientation different from the first crystal orientation ("an epitaxial end cap with a first crystal orientation disposed on a sidewall of the nanostructured layer and on a sidewall of the inner spacer; an epitaxial base with a second crystal orientation different from the first crystal orientation disposed in the fin base", in claim 17 of Pat '335, is interpreted as the same limitation), for the purpose of providing multi-step epitaxial source/drain structures to improve device performance, reliability, and yield.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '638 in view of Lee to have the first region comprising a first crystal orientation, and wherein the second region comprises a second crystal orientation different from the first crystal orientation, as taught by claim 17 of Pat '335, for the purpose of providing multi-step epitaxial source/drain structures to improve device performance, reliability, and yield. as described above.
Claims 17-20 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2 and 8 of U.S. Patent No. 12,170,335 in view of Tsai (US 2021/0234047).
Regarding claim 17, Pat '335 discloses, in claim 1, a method, comprising:
forming a stack of first and second layers arranged in an alternating configuration on a substrate; forming spacers on sidewalls of the first layers; forming a first layer on sidewalls of the second layers and the spacers; removing portions of the first layer to expose sidewalls of the spacers and form epitaxial caps on the second layers; and epitaxially growing a second layer on the epitaxial caps ("forming a stack of first and second semiconductor layers arranged in an alternating configuration on a substrate; etching the substrate to form an opening adjacent to the stack of first and second semiconductor layers; forming inner spacers on sidewalls of the first semiconductor layers; forming a first epitaxial layer with first epitaxial portions on sidewalls of the second semiconductor layers, second epitaxial portions on sidewalls of the inner spacers, and a third epitaxial portion in the opening, wherein the first epitaxial portions are thicker than the second epitaxial portions; performing an etching process on the first epitaxial layer; forming a second epitaxial layer on the first epitaxial layer" and “performing the etching process comprises etching the second epitaxial portions to expose the sidewalls of the inner spacers”, in claims 1 and 2 of Pat '335, are interpreted as the same limitation).
Pat '335 does not explicitly disclose a stack of first and second nanostructured layers; a first semiconductor layer on sidewalls of the second nanostructured layers and the spacers; a second semiconductor layer on the epitaxial caps.
Tsai teaches, in at least figures 12-14 and related text, the method comprising a stack of first (206, [15]) and second (208, [15]) nanostructured layers; a first semiconductor layer (240, [29]) on sidewalls of the second nanostructured layers (208, [15]) and the spacers (238, [29]); a second semiconductor layer (242, [30]) on the epitaxial caps (240, [29]), for the purpose of providing multi-gate transistors having a diffusion retardation layer to prevent leakage ([10]).
Pat '335 and Tsai are analogous art because they are directed to method for forming a semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '335 with the specified features of Tsai because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '335 to have the stack of first and second nanostructured layers; the first semiconductor layer on sidewalls of the second nanostructured layers and the spacers; the second semiconductor layer on the epitaxial caps, as taught by Tsai, for the purpose of providing multi-gate transistors having a diffusion retardation layer to prevent leakage ([10], Tsai).
Regarding claim 18, Pat '335 in view of Tsai discloses the method of claim 17 as described above.
Tsai further teaches, in at least figures 12-14 and related text, epitaxially growing the first semiconductor layer (240, [29]) on the second nanostructured layers (208, [15]), for the purpose of providing multi-gate transistors having a diffusion retardation layer to prevent leakage ([10]).
Regarding claim 19, Pat '335 in view of Tsai discloses the method of claim 17 as described above.
Pat '335 further discloses, in claim 1, forming a first layer portion with a first thickness on the second nanostructured layers; and forming a second layer portion with a second thickness on the spacers, wherein the first thickness is greater than the first thickness ("forming a first epitaxial layer with first epitaxial portions on sidewalls of the second semiconductor layers, second epitaxial portions on sidewalls of the inner spacers, and a third epitaxial portion in the opening, wherein the first epitaxial portions are thicker than the second epitaxial portions", in claim 1 of Pat '335, is interpreted as the same limitation).
Regarding claim 20, Pat '335 in view of Tsai discloses the method of claim 17 as described above.
Pat '335 further discloses, in claim 8, forming an oxide layer on the stack of first and second semiconductor layers and in contact with one of the epitaxial caps ("forming an oxide layer on the stack of first and second semiconductor layers and in contact with one of the first epitaxial portions", in claim 8 of Pat '335, is interpreted as the same limitation).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 and 5-8 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Wang (US 2021/0343639).
Regarding claim 1, Wang discloses, in at least figure 13A and related text, a semiconductor device, comprising:
a substrate (112, [38]);
a plurality of nanostructures (124, [62]) disposed on the substrate (112, [38]);
a gate structure (220, [64]) disposed on the plurality of nanostructures (124, [62]);
a source/drain region (192/194, [58]), comprising:
a first source/drain portion (192, [58]) comprising a dopant, and
a second source/drain portion (194, [58]) comprising the dopant and in contact with the first source/drain portion (192, [58]), wherein a concentration of the dopant in the first source/drain portion is different from a concentration of the dopant in the second source/drain portion ([58]); and
a dielectric layer (162, [45]) disposed on one of the nanostructures of the plurality of nanostructures (124, [62]) and in contact with the first source/drain portion (192, [58]).
Regarding claim 2, Wang discloses the semiconductor device of claim 1 as described above.
Wang further discloses, in at least figure 13A and related text, the second source/drain portion (194, [58]) is disposed on a sidewall of a spacer (170, [48]) disposed on the gate structure (220, [64]).
Regarding claim 3, Wang discloses the semiconductor device of claim 1 as described above.
Wang further discloses, in at least figure 13A and related text, the first source/drain portion (192, [58]) comprises curved sidewall profiles.
Regarding claim 5, Wang discloses the semiconductor device of claim 1 as described above.
Wang further discloses, in at least figure 13A and related text, the first source/drain portion (192, [58]) is in contact with a sidewall of the dielectric layer (162, [45]).
Regarding claim 6, Wang discloses the semiconductor device of claim 1 as described above.
Wang further discloses, in at least figure 13A and related text, a third source/drain portion (192, [58]) disposed in the substrate (112, [38]) and under the second source/drain portion (194, [58]), wherein the first (192, [58]) and third (192, [58]) source/drain portions comprise a same material.
Regarding claim 8, Wang discloses the semiconductor device of claim 1 as described above.
Wang further discloses, in at least figure 13A and related text, the second source/drain portion (194, [58]) comprises a dopant concentration profile that decreases from a top surface of the second source/drain portion to a bottom surface of the second source/drain portion ([58]).
Claim(s) 11-13 and 15-16 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Lee (US 2021/0126135).
Regarding claim 11, Lee discloses, in at least figure 32B and related text, a semiconductor device, comprising:
a substrate (100, [9]);
a plurality of nanostructures (108, [12]) disposed on the substrate (100, [9]);
a source/drain region (160, [45]) in contact with the plurality of nanostructures (108, [12]);
a gate structure (170, [33]) surrounding the plurality of nanostructures (108, [12]) and comprising a gate spacer (131, [26]) disposed on the nanostructures (108, [12]); and
a dielectric layer (121, [22]) disposed between the gate spacer (131, [26]) and one of the nanostructures (108, [12]) of the plurality of nanostructures (108, [12]) and in contact with the source/drain region (160, [45]).
Regarding claim 12, Lee discloses the semiconductor device of claim 11 as described above.
Lee further discloses, in at least figure 32B and related text, the source/drain region (160, [45]) comprises first (162 on 108, [45], figure), second (162 on 150, [45], figure), and third (164, [45]) regions, and wherein a portion of the third region (164, [45]) is disposed between the first (162 on 108, [45], figure) and second (162 on 150, [45], figure) regions.
Regarding claim 13, Lee discloses the semiconductor device of claim 12 as described above.
Lee further discloses, in at least figure 32B and related text, the second region (162 on 150, [45], figure) comprises top and bottom surfaces with curved profiles.
Regarding claim 15, Lee discloses the semiconductor device of claim 12 as described above.
Lee further discloses, in at least figure 32B and related text, the first region (162 on 108, [45], figure) and the plurality of nanostructures (108, [12]) comprise a same crystal orientation ([43]).
Regarding claim 16, Lee discloses the semiconductor device of claim 12 as described above.
Lee further discloses, in at least figure 32B and related text, the second region (162 on 150, [45], figure) and the substrate (100, [37]) comprise a same crystal orientation ([43]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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/TONG-HO KIM/ Primary Examiner, Art Unit 2811
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