DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/15/2024 was filed after the mailing date of the application. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-8, 10-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,087,768, hereinafter ‘768. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-20 of ‘768 disclose limitations of claims 1-8, 10-20 of present application.
Regarding claim 1, Claims 1 and 4 of ‘768 discloses:
A semiconductor device structure, comprising:
first nanostructures and second nanostructures stacked in a vertical direction over a substrate,
a first dielectric structure between the first nanostructures and the second nanostructures, and
a first gate structure formed over the first nanostructures, wherein the first gate structure comprises a gate dielectric layer, and a topmost surface of the gate dielectric layer is higher than a top surface of the first dielectric structure (lines 40-50, and lines 62-64, Col. 22).
Regarding claim 2, Claims 7 and 8 of ‘768 disclose the structure as claimed in claim 1, further comprising:
a second dielectric structure formed adjacent to the second nanostructures, wherein a width of the second dielectric structure is greater than a width of the first dielectric structure (lines 9-18, Col. 23).
Regarding claim 3, Claim 13 of ‘768 discloses wherein the second dielectric structure has a -shaped structure (lines 62-65, Col. 23).
Regarding claim 4, Claims 7 and 9 of ‘768 disclose the structure as claimed in claim 2, further comprising:
a first isolation structure formed below the first dielectric structure, and
a second isolation structure formed below the second dielectric structure, wherein a width of the second isolation structure is greater than a width of the first isolation structure (lines 16-25, Col. 23).
Regarding claim 5, Claims 1 and 2 of ‘768 disclose the structure as claimed in claim 2, further comprising: a capping layer formed over the second dielectric structure, wherein the gate dielectric layer is in direct contact with a sidewall surface of the capping layer (lines 51-55, Col. 22).
Regarding claim 6, Claim 11 of ‘768 discloses the structure as claimed in claim 1, further comprising: a gate spacer layer formed adjacent to the first gate structure, wherein a portion of the first dielectric structure is directly below the gate spacer layer (lines 45-55, Col. 23).
Regarding claim 7, Claim 10 of ‘768 discloses the structure as claimed in claim 1, further comprising: a first S/D structure formed adjacent to the first gate structure, wherein a top surface of the first S/D structure is higher than a top surface of the first dielectric structure (lines 28-40, Col. 23).
Regarding claim 8, Claim 10 of ‘768 discloses the structure as claimed in claim 7, further comprising an S/D structure. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have S/D contact formed on the S/D structure to provide electrical connection between the S/D region and overlying interconnect/conductive structure.
Regarding claim 10, Claims 10 and 13 of ‘768 disclose the structure a semiconductor device structure, comprising:
an isolation structure formed over a substrate,
a first nanostructures and a second nanostructures extending above the isolation structure,
a first S/D structure formed adjacent to the first nanostructure,
a second S/D structure formed adjacent to the second nanostructure, and
a first dielectric structure formed over the isolation structure, wherein the first dielectric structure is between the first S/D structure and the second S/D structure, and between the first nanostructures and the second nanostructures, wherein first dielectric structure has a U-shaped structure, and a filling layer is formed in a recessed portion of the U-shaped structure (lines 27-43, 62-65, Col. 23).
Regarding claim 11, Claim 15 of ‘768 discloses the structure as claimed in claim 10, further comprising: an inner spacer layer formed adjacent to the first nanostructures, wherein the inner spacer layer is in direct contact with the first dielectric structure (lines 6-11, Col. 24).
Regarding claim 12, Claim 11 of ‘768 discloses the structure as claimed in claim 10, further comprising: a first gate structure formed adjacent to the first S/D structure, and a gate spacer layer formed adjacent to the first gate structure, wherein a portion of the first dielectric structure is directly below the gate spacer layer (lines 44-55, Col. 23).
Regarding claim 13, Claim 12 of ‘768 discloses the structure as claimed in claim 12, further comprising: a hard mask layer formed over the first nanostructures, wherein the hard mask layer is directly below the gate spacer layer (lines 56-61, Col. 23).
Regarding claim 14, Claims 7 and 8 of ‘768 discloses the structure as claimed in claim 12, further comprising: a second dielectric structure formed adjacent to the first dielectric structure, wherein a width of the second dielectric structure is greater than a width of the first dielectric structure (lines 20-25, Col. 23).
Regarding claim 15, Claim 14 of ‘768 discloses the structure as claimed in claim 12, further comprising: a capping layer formed over the first dielectric structure, wherein the capping layer and the first dielectric structure are made of different materials (lines 1-5, Col. 24).
Regarding claim 16, Claims in ‘768 fails to disclose wherein an interface between the first dielectric structure and the capping layer is lower than a top surface of a topmost first nanostructure. It would have been obvious to one having ordinary skill in the art at the time the invention was made to vary the height of the structure through routine experimentation and optimization in order to obtain a desired device configuration and performance, since optimization of a variable is ordinarily within the skill in the art.
Regarding claim 17, Claims 1, 4, and 15 of ‘768 disclose a semiconductor device structure comprising:
first nanostructures and second nanostructures formed along a first direction over a substrate,
a first dielectric structure between the first nanostructures and the second nanostructures formed along the first direction,
a first gate structure formed over the first nanostructures,
a first gate spacer layer formed adjacent to the first gate structure, and
an inner spacer layer directly below the first gate spacer layer, wherein a topmost surface of the inner spacer layer is higher than a top surface of the first dielectric structure (lines 40-50, and lines 62-64, Col. 22, lines 6-11, Col. 24).
Regarding claim 18, Claim 15 of ‘768 discloses the structure as claimed in claim 10, further comprising: an inner spacer layer formed adjacent to the first nanostructures, wherein the inner spacer layer is in direct contact with the first dielectric structure (lines 6-11, Col. 24).
Regarding claim 19, Claim 12 of ‘768 discloses the structure as claimed in claim 12, further comprising: a hard mask layer formed over the first nanostructures, wherein the hard mask layer is directly below the gate spacer layer (lines 56-61, Col. 23).
Regarding claim 20, Claims 7-8, 19-20 of ‘768 disclose the structure as claimed in claim 17, further comprising: a second dielectric structure formed adjacent to the first dielectric structure, wherein a width of the second dielectric structure is greater than a width of the first dielectric structure, and a third dielectric structure (third fin structure) formed adjacent to the second dielectric structure, wherein a width of the third dielectric structure is greater than a width of the second dielectric structure (lines 10-20, Col. 23; lines 55-65, Col. 24).
Claim 9 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,087,768 in view of Ching et al., U.S. 10,483,378.
Regarding claim 9, Claim 1 of ‘768 fails to disclose a contact etch stop layer formed on and in direct contact with the first dielectric structure. Ching discloses the etch stop layer 115 over dielectric fins 108 (Fig. 11, [0044]). It would have been obvious to one having ordinary skill in the art at the time the invention was made to use etch stop layer on and in contact with dielectric structure in order to provide an etch stop layer during subsequent contact formation and thereby protect the underlying device from etching.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THAO P LE whose telephone number is (571)272-1785. The examiner can normally be reached on Monday-Friday 9AM-6PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
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/THAO P LE/Primary Examiner, Art Unit 2818
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