DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a Non-Final office action based on application 18/773,250 filed July 15, 2024. Claims 1-20 are currently pending and have been considered below.
Claim Objections
Claim 8 is objected to because of the following informalities: Claim 8 has a limitation of “a via extending through the semiconductor layer to the second dielectric layer and electrically connected to a third contact in the wiring layer and the inductor” however the “second dielectric layer” in the claim refers to the capacitor dielectric (50) and the via does not extend to the capacitor dielectric but instead extend to the claimed “first dielectric layer” in which the inductor is embedded. Appropriate correction is required. Further claims 9-15 are also objected based on their dependency from claim 8.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 5-7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ramachandran (Pre-Grant Publication 2015/0250058).
Regarding claim 1, Ramachandran discloses a semiconductor device comprising:
a first dielectric layer (Fig. 3, 311;Paragraph [0049]) disposed over a second dielectric layer (362; Paragraph [0058]);
a wiring layer (360) disposed over an opposing side of the first dielectric layer from the second dielectric layer;
a capacitor (330) embedded in the first dielectric layer, wherein the capacitor comprises a first electrode (318) electrically connected to a first contact in the wiring layer, a second electrode (332) electrically connected to a second contact in the wiring layer, and a third dielectric layer (322) disposed between the first electrode and the second electrode,
a via (308) extending through the first dielectric layer to the second dielectric layer and electrically connected to a third contact in the wiring layer; and
a chip (380-1/380-2) disposed over an opposing side of the wiring layer from the first dielectric layer.
Regarding claim 2, Ramachandran further discloses:
the capacitor is a deep trench capacitor (Paragraph [0049]).
Regarding claim 5, Ramachandran further discloses:
a substrate (190), wherein an opposing side of the second dielectric layer from the first dielectric layer faces the substrate.
Regarding claim 6, Ramachandran further discloses:
the substrate is bonded to the second dielectric layer through a plurality of solder bumps (302).
Regarding claim 7, Ramachandran further discloses:
the chip (380-1/380-2) forms a system on a chip package (Paragraph [0049]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ramachandran (Pre-Grant Publication 2015/0250058) in view of Muri (Pre-Grant Publication 2018/0374843).
Regarding claim 3 & 4, Ramachandran disclose all of the limitations of claim 1 & 2 (addressed above). Ramachandran does not explicitly disclose the trench depth of the trench capacitor is 20-50 microns or the first dielectric layer has a thickness of 100-300 microns. However Muri discloses a semiconductor device comprising:
Deep trench capacitors (Fig. 1a, 30) formed in a support structure (15) wherein the depth of the trenches can be 20-50 microns and the thickness of 10-200 microns (Paragraph [0024] & [0029]).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the trench capacitor to a depth of 20-50 microns and the support structure to thickness of 10-200 microns because it will allow the capacitor to be formed with a high aspect ratio thereby increasing the capacitance of the capacitors (Paragraph [0029]) and the support structure will provide mechanical stability (Paragraph [0024]).
Allowable Subject Matter
Claims 16-20 are allowed.
The following is an examiner’s statement of reasons for allowance: Claim 16 is allowed because none of the prior art either alone or in combination discloses: a semiconductor layer disposed over a first dielectric layer; a wiring layer disposed over an opposing side of the semiconductor layer from the first dielectric layer; a plurality of deep trench capacitors embedded in the semiconductor layer, a plurality of magnetic core inductors embedded in the first dielectric layer; a via extending through the semiconductor layer and electrically connecting the wiring layer and the magnetic core inductors; and a chip disposed over an opposing side of the wiring layer from the first dielectric layer and electrically connected to the first wiring layer. Claims 17-20 are also allowed based on their dependency from claim 16.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Dogiamis (Pre-Grant Publication 2020/0075491) disclose a microelectronic device comprising ferroelectric capacitors embedded in a package substrate and a inductor coupled between the capacitors.
Raorane (Pre-Grant Publication 2019/0287956) disclose a recessed semiconductor die in a stacked die wherein the recessed die can be a inductor.
Zhao (Pre-Grant Publication 2015/0302974) disclose a 3D packaging device comprising a magnetic core inductor embedded in a package substrate and coupled to an active chip on the package substrate.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRANDON C FOX whose telephone number is (571)270-5016. The examiner can normally be reached M-F 9:00AM-6:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff W Natalini can be reached at 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRANDON C FOX/Examiner, Art Unit 2818
/DAVID VU/Primary Examiner, Art Unit 2818
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