DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 7 and 15 are objected to because of the following informalities:
The verb “isolated” in claims 7 and 15 should be “is isolated”.
The limitation “the enable signal” in claim 19, line 4 should be “the write enable signal”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7 and 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 7 and 15 each recite the limitation “wherein the capacitor isolated after the word line activation signal.”. Since the capacitor has two terminals, it is unclear from what element the capacitor is isolated.
Claim 18 recites the limitations "the first bit line" and “the second bit line” in line 7 and “the write driver circuit” in lines 8-9. There is insufficient antecedent basis for each of these limitations in the claim.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-7 of U.S. Patent No. 12,073,867. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-17 would have been obvious over claims 1-7 of the patent.
Regarding claims 1 and 10, claims 1, 2 and 7 of the patent recites a memory device, comprising:
a memory cell array comprising a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns, wherein each of the plurality of columns comprises a first plurality of memory cells connected to a first bit line and a second bit line, and wherein each of the first plurality of memory cells comprising:
a first invertor connected between a first node and a second node, and
a second invertor connected between the first node and the second node, wherein the first invertor and the second invertor are cross coupled at a first data node and a second data node (claim 2);
a pull down line (a line between the second node and the pull down circuit), wherein the second node of each of the first plurality of memory cells is connected to the pull down line;
a pull down circuit connected to the pull down line, wherein the pull down circuit is operative to pull down a voltage of the second node through the pull down line below a ground voltage in response to receiving an enable signal (claim 1).
It would have been obvious to one having ordinary skill in the art to recognize that the plurality of bit cells are in a column of a memory array arranged in a memory array and the negative voltage generator circuit considered as the pull down circuit is connected to the second node by a pull down line.
Regarding claim 2, claims 1, 2 and 7 of the patent do not recite that the memory device of claim 1 and claim 11, further comprising a select circuit connected between the pull down circuit and the pull down line, wherein the select circuit is operative to connect the pull down circuit to the pull down line. However, the use of a select circuit to connect or disconnect two elements are well-known in the art. It would have been obvious to one having ordinary skill in the art to use a select circuit to connect or disconnect the pull down circuit to or from the pull down line.
Regarding claims 3 and 12, claim 3 of the patent recites the memory device of claim 1 and claim 10, wherein the pull down circuit comprises a negative voltage generator circuit comprising a capacitor connected to the second node, and wherein the capacitor is operative to pull down the voltage of the second node below the ground voltage in response to the enable signal.
Regarding claims 4 and 13, claim 4 of the patent recites the memory device of claim 3 and claim 12, wherein the capacitor comprises a Metal Oxide Semiconductor (MOS) capacitor.
Regarding claim 5, claim 5 of the patent recites the memory device of claim 3 and claim 12, wherein the capacitor comprises a plurality of metal plates substantially parallel to each other.
Regarding claims 6 and 14, claim 1 of the patent recites the memory device of claim 3 and claim 12, wherein the enable signal is activated before a word line activation signal, the word line activation signal indicating a read operation on the memory device.
Regarding claims 7 and 15, claim 6 of the patent recites the memory device of claim 3 and claim 12, wherein the capacitor isolated after the word line activation signal.
Regarding claims 8 and 16, claim 1 of the patent recites the memory device of claim 1 and claim 10, wherein the enable signal is activated before a word line activation signal, the word line activation signal indicating a write operation on the memory device.
Regarding claim 9 and 17, claim 7 of the patent recites the memory device of claim 1 claim 10, wherein the pull down circuit is shared by a plurality of bit cells.
Claims 1-17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2 and 4-8 of U.S. Patent No. 11,600,317 in view of Kawamusi (US 8,379,436)
Regarding claims 1, 9, 10 and 17, claim 1 recites a memory device, comprising:
a bit cell comprising:
a first invertor connected between a first node and a second node, and
a second invertor connected between the first node and the second node, wherein the first invertor and the second invertor are cross coupled at a first data node and a second data node;
a pull down line (the line from the second node to the pull down circuit), wherein the second node is connected to the pull down line;
a pull down circuit connected to the pull down line, wherein the pull down circuit is Operative to pull down a voltage of the second node through the pull down line below a ground voltage in response to receiving an enable signal.
Claim 1 does not recite a memory device comprising a memory array and the second node of each of the plurality of memory cells connected to the pull down line. However, Kawasumi discloses the use of a power supply booster 15 (Fig. 16) to individually boost the power supply voltages of the memory cells in each column. It would have been obvious to one having ordinary skill in the art to use a power supply booster to boost the power supply voltage for the memory cells in each column.
Regarding claims 2 and 11, claim 1 of the patent does not recite that the memory device of claim 1 and claim 10, further comprising a select circuit connected between the pull down circuit and the pull down line, wherein the select circuit is operative to connect the pull down circuit to the pull down line. However, the use of a select circuit to connect or disconnect two elements are well-known in the art. It would have been obvious to one having ordinary skill in the art to use a select circuit to connect or disconnect the pull down circuit to or from the pull down line.
Regarding claims 3 and 12, claim 2 of the patent recites the memory device of claim 1 and claim 10, wherein the pull down circuit comprises a negative voltage generator circuit comprising a capacitor connected to the second node, and wherein the capacitor is operative to pull down the voltage of the second node below the ground voltage in response to the enable signal.
Regarding claims 4 and 13, claim 4 of the patent recites the memory device of claim 3 and claim 12, wherein the capacitor comprises a Metal Oxide Semiconductor (MOS) capacitor.
Regarding claims 5, claim 5 of the patent recites the memory device of claim 3, wherein the capacitor comprises a plurality of metal plates substantially parallel to each other.
Regarding claims 6 and 14, claim 6 of the patent recites the memory device of claim 3 and claim 12, wherein the enable signal is activated before a word line activation signal, the word line activation signal indicating a read operation on the memory device.
Regarding claims 7 and 15, claim 7 of the patent recites the memory device of claim 3 and 12, wherein the capacitor isolated after the word line activation signal.
Regarding claims 8 and 16, claim 8 of the patent recites the memory device of claim 1 and claim 10, wherein the enable signal is activated before a word line activation signal, the word line activation signal indicating a write operation on the memory device.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 9 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kawasumi.
Regarding claims 1 and 10, Kawasumi discloses a memory device, comprising:
a memory cell array (Fig. 12) comprising a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns, wherein each of the plurality of columns comprises a first plurality of memory cells connected to a first bit line and a second bit line, and wherein each of the first plurality of memory cells (Fig. 13) comprising:
a first invertor (P1 and N3) connected between a first node (PWN) and a second node (VN), and
a second invertor (P2 and N4) connected between the first node and the second node, wherein the first invertor and the second invertor are cross coupled at a first data node (NDt) and a second data node (NDc);
a pull down line (line connects VN to transistor N12), wherein the second node of each of the first plurality of memory cells is connected to the pull down line (column 4, lines 25-29);
a pull down circuit (Fig. 16) connected to the pull down line, wherein the pull down circuit is operative to pull down a voltage of the second node through the pull down line below a ground voltage (VSSL<VSS) in response to receiving an enable signal (signal from the output of inverter N11).
Regarding claim 9, Kawasumi discloses the memory device of claim 1, wherein the pull down circuit is shared by a plurality of bit cells (column 4, lines 25-29).
Claims 1, 3, 4, 9, 10, 12 and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Braceras et al. (US 9,236,116, hereinafter “Braceras”).
Regarding claims 1 and 10, Braceras discloses a memory device, comprising:
a memory cell array (Fig. 1) comprising a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns, wherein each of the plurality of columns comprises a first plurality of memory cells connected to a first bit line and a second bit line, and wherein each of the first plurality of memory cells comprising:
a first invertor connected between a first node and a second node, and
a second invertor connected between the first node and the second node, wherein the first invertor and the second invertor are cross coupled at a first data node and a second data node;
a pull down line (line connects the second node to Vboost1), wherein the second node of each of the first plurality of memory cells is connected to the pull down line (column 3, lines 55-56);
a pull down circuit (Fig. 3) connected to the pull down line, wherein the pull down circuit is operative to pull down a voltage of the second node through the pull down line below a ground voltage (VBOOST signal is negative) in response to receiving an enable signal (WBOOSTP).
Regarding claims 3 and 12, Braceras (Fig. 3, 100) discloses the memory device of claim 1 and claim 10, wherein the pull down circuit comprises a negative voltage generator circuit comprising a capacitor connected to the second node, and wherein the capacitor is operative to pull down the voltage of the second node below the ground voltage in response to the enable signal.
Regarding claims 4 and 13, Braceras (Fig. 3) shows the memory device of claim 3 and claim 12, wherein the capacitor comprises a Metal Oxide Semiconductor (MOS) capacitor.
Regarding claim 9, Braceras discloses the memory device of claim 1, wherein the pull down circuit is shared by a plurality of bit cells (column 3, lines 55-56).
Claims 1, 9 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US 7,701,755, herein after “Chen”).
Regarding claims 1 and 10, Chen discloses a memory device, comprising:
a memory cell array (Fig. 1) comprising a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns, wherein each of the plurality of columns comprises a first plurality of memory cells connected to a first bit line and a second bit line, and wherein each of the first plurality of memory cells comprising:
a first invertor connected between a first node and a second node, and
a second invertor connected between the first node and the second node, wherein the first invertor and the second invertor are cross coupled at a first data node and a second data node (Fig. 2);
a pull down line (Fig. 2, line connects the second node to Negative VSS), wherein the second node of each of the first plurality of memory cells is connected to the pull down line;
a pull down circuit (Fig. 2, 32) connected to the pull down line, wherein the pull down circuit is operative to pull down a voltage of the second node through the pull down line below a ground voltage (Negative VSS) in response to receiving an enable signal (R_assit [n-1]).
Regarding claims 9 and 17, Braceras discloses the memory device of claim 1, wherein the pull down circuit is shared by a plurality of bit cells (Fig. 2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 17 /are rejected under 35 U.S.C. 103 as being unpatentable over Kawamusi or Braceras.
The only difference between claims 2 and 17 and Kawamuchi or Braceras is that
the memory device further comprises a select circuit connected between the pull down circuit and the pull down line, wherein the select circuit is operative to connect the pull down circuit to the pull down line. However, the use of a select circuit to connect or disconnect two elements are well-known in the art. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use a select circuit to connect or disconnect the pull down circuit to or from the pull down line.
Conclusion
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/HUAN HOANG/Primary Examiner, Art Unit 2827