CTNF 18/773,342 CTNF 84055 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The information disclosure statement (IDS) submitted on July 15, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Drawings The following figures are objected to for being non-enabled or inoperable due to hard wired permanent electrical shorts shorting all of the bit lines of a memory array (see the output of circuit 108 drawn as a hard wire that shorts all of the bit lines of the memory array together): Figure 1 and Figure 4. Hard wire connections are drawn that permanently short not only each bit line with its complementary bit line but also shorts all of the bit line pairs with each other across the entire memory array at the output of circuit 108 in each of the figures. Hence, the memory array in each instance is NOT expected, by one of ordinary skill in the art, to properly work since data stored in the array will NOT be successfully read from the memory array and data will NOT be successfully written to the memory array. Each of these figures is a non-working or inoperable embodiment. Corrected drawings are requested. No new matter should be entered. 06-27 AIA In addition to Replacement Sheets containing the corrected drawing figure(s), applicant is required to submit a marked-up copy of each Replacement Sheet including annotations indicating the changes made to the previous version. The marked-up copy must be clearly labeled as “Annotated Sheets” and must be presented in the amendment or remarks section that explains the change(s) to the drawings. See 37 CFR 1.121(d)(1). Failure to timely submit the proposed drawing and marked-up copy will result in the abandonment of the application. Specification 07-29 AIA The disclosure is objected to because of the following informalities: Regarding the phrase “assist circuits 108”: This phrase appears 14 times but is erroneous since there is only one circuit 108 in each of Figure 1 and Figure 4. Regarding [0039]: Change “In some example” to “In some examples”. Regarding [0043]: Change “inly two transistors” to “only two transistors” . Appropriate correction is required. Claim Objections 07-29-01 AIA Claim s 1 and 15 objected to because of the following informalities: Regarding claim 1: Change “between pre-charge circuit” to “between the pre-charge circuit”. Regarding claim 15: Change “comprises two or more transistors are connected in parallel” to “comprises two or more transistors connected in parallel” . Appropriate correction is required. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. 08-36 AIA Claim s 1-6 and 17-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1-3, 5-6, 17-20 of U.S. Patent No. US 12,080,342 (hereinafter “reference patent”) in view of Hong (US 20200075089) and Goetz (US 2008/0123448) . Regarding claim 1: Claim 1 of the reference patent teaches a memory device, comprising: a memory cell array comprising a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns, wherein each of the plurality of columns comprises a first plurality of memory cells connected to a first bit line and a second bit line (identical to language of claim 1 of the reference patent; hence, anticipated) ; a pre-charge circuit connected to the memory cell array, wherein the pre-charge circuit pre-charges each of the first bit line and the second bit line from a first end (identical to language of claim 1 of the reference patent; hence, anticipated) ; and a second circuit (a pre-charge assist circuit) that pre-charges each of the first bit line and the second bit line from a second end. Claim 1 does not specifically teach the second circuit comprises at least one transistor connected between [the] pre-charge circuit and the second end of each of the first bit line and the second bit line, wherein the at least one transistor pre-charges each of the first bit line and the second bit line from the second end. Hong (FIGs. 1-4) teaches a bit line precharge device 102 arranged at a bottom of a memory array, wherein the precharge device 102 precharges the bit lines of the memory array from a first end (bottom end), and a precharge signal (BLPCH) transits across the precharge deice 102. Goetz (FIG. 2; [0002-0004, 0019-0022]) teaches concurrently pre-charging a bit line of a memory array from both ends, wherein a PMOS transistor (224 1 ) is connected at the far end or top end of a bit line and is controlled by the same control signal as the pre-charge circuit at the near or bottom end. Goetz discloses that pre-charging the bit line from both ends reduces the pre-charging time. It would have been obvious to one of ordinary skill in the art to incorporate the teaching of Hong and Goetz into the device and/or method of claim 1 of the reference patent in a manner such that the second circuit would comprise PMOS transistors like that taught by Goetz that would be arranged at the second end (top end of the memory array) of the bit lines, wherein each of the PMOS transistors would have an upper source terminal connected to a pre-charge voltage VDD (VDD is known to refer to a high level supply voltage as exemplified in [0020, 0024] of Hong) , a gate connected to control signal BLPCH after BLPCH traverses horizontally across the precharge circuit 102 as seen in FIG. 4 of Hong, and a lower drain terminal directly connected to a respective bit line of the array (BL or BLB; each bit line, regardless of whether it is a BL or BLB would pre-charged via a corresponding PMOS transistor of the PMOS transistors being added from Goetz) to pre-charge each bit line from the top end in response to the bit line pre-charge control signal BLPCH such that each bit line would be pre-charged from the top end by the PMOS transistors while the bit line precharge device 102 pre-charges the same bit lines from the lower end. Note that the at least one transistor (the PMOS transistors at the top of the memory array) are considered to be connected between pre-charge circuit 102 and a second end (top end) of each of the first bit line and the second bit line because the control signal BLPCH transits across102 and then to the control gates of the at least one PMOS transistor from Goetz in the same fashion as that illustrated in Applicant’s figures Figure 1, Figure 4, and Figure 5. The motivation to do so would have been to enjoy the benefits disclosed by Goetz such as reducing the pre-charge time of the memory array ([0019-0022] of Goetz) in preparation for a data reading operation or a data writing operation (see [0002] of Goetz) . Regarding claim 2: In so far as definite, Claim 2 of the reference patent teaches the subject matter of this claim, wherein “the transistor” is interpreted to mean “the at least one transistor” introduced in claim 1. Regarding claim 3: In so far as definite, Claim 3 of the reference patent teaches the subject matter of this claim, wherein “the transistor” is interpreted to mean “the at least one transistor” introduced in claim 1. Regarding claim 4: In so far as definite, Claim 1 as modified above teaches the at one transistor comprises a PMOS, wherein “the transistor” is interpreted to mean “the at least one transistor” introduced in claim 1. Regarding claims 5-6: In so far as definite, Claims 5-6 of the reference patent teaches the subject matter of these claims, respectively, wherein “the pre-charge assist circuit” is interpreted to mean “the at least one transistor” introduced in claim 1. Regarding claim 17: Claim 17 of the reference patent teaches a method of pre-charging bit lines of a memory device, the method comprising: providing a first plurality of memory cells arranged in a first column of a memory cell array (identical to language of claim 17 of the reference patent; hence, anticipated) ; providing a first bit line connected to each of the first plurality memory cells (identical to language of claim 17 of the reference patent; hence, anticipated) ; providing a first complementary bit line connected to each of the first plurality of memory cells (identical to language of claim 17 of the reference patent; hence, anticipated) ; pre-charging both the first bit line and the first complementary bit line from a near end through a pre-charge circuit, wherein the pre-charge circuit is connected to the near end of each of the first bit line and the first complementary bit line (identical to language of claim 17 of the reference patent; hence, anticipated) ; and pre-charging both the first bit line and the first complementary bit line from a far end through a second circuit (a pre0charge assist circuit), wherein the second circuit is connected to the far end of each of the first bit line and the first complementary bit line (see last claim element of claim 17 of the reference patent) . Claim 17 of the reference patent does not specifically teach the second circuit comprises at least one transistor, wherein the at least one transistor is connected to the pre-charge circuit and the far end of each of the first bit line and the first complementary bit line. Hong (FIGs. 1-4) teaches a bit line precharge device 102 arranged at a bottom of a memory array, wherein the precharge device 102 precharges the bit lines of the memory array from a first end (bottom end), and a precharge signal (BLPCH) transits across the precharge deice 102. Goetz (FIG. 2; [0002-0004, 0019-0022]) teaches concurrently pre-charging a bit line of a memory array from both ends, wherein a PMOS transistor (224 1 ) is connected at the far end or top end of a bit line and is controlled by the same control signal as the pre-charge circuit at the near or bottom end. Goetz discloses that pre-charging the bit line from both ends reduces the pre-charging time. It would have been obvious to one of ordinary skill in the art to incorporate the teaching of Hong and Goetz into the device and/or method of claim 17 of the reference patent in a manner such that the second circuit would comprise PMOS transistors that would be arranged at the second end (top end of the memory array) of the bit lines, wherein each of the PMOS transistors would have an upper source terminal connected to a pre-charge voltage VDD (VDD is known to refer to a high level supply voltage as exemplified in [0020, 0024] of Hong) , a gate connected to control signal BLPCH after BLPCH traverses horizontally across the precharge circuit 102 as seen in FIG. 4 of Hong, and a lower drain terminal directly connected to a respective bit line of the array (BL or BLB; each bit line, regardless of whether it is a BL or BLB would pre-charged via a corresponding PMOS transistor of the PMOS transistors being added) to pre-charge each bit line from the top end in response to the bit line pre-charge control signal BLPCH such that each bit line would be pre-charged from the top end by the PMOS transistors while the bit line precharge device 102 pre-charges the same bit lines from the lower end. Note that the at least one transistor (the PMOS transistors at the top of the memory array) are considered to be connected between pre-charge circuit 102 and a second end (top end) of each of the first bit line and the second bit line because the control signal BLPCH transits across 102 and then to the control gates of the at least one PMOS transistor from Goetz in the same fashion as that illustrated in Applicant’s figures Figure 1, Figure 4, and Figure 5. The motivation to do so would have been to enjoy the benefits disclosed by Goetz such as reducing the pre-charge time of the memory array ([0019-0022] of Goetz) in preparation for a data reading operation or a data writing operation (see [0002] of Goetz) . Regarding claims 18-20: Claims 18-20 of the reference patent, respectively, teach the subject matter of these claims. Claims 7-8 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 2 of the reference patent ( US 12,080,342) as modified by Hong (US 20200075089) and Goetz (US 2008/0123448) in view of Yang et al. (US 2014/0269021; hereinafter “Yang”). Regarding claim 7: Claim 2 of the reference as modified by Hong and Goetz already teaches that a pre-charge of bit lines is performed in preparation for a data reading or writing operation (see [0002] of Goetz) ; however, does not specifically teach the pre-charge assist signal is associated with a read enable signal. Yang ([0055]) states “a desire to perform a read operation is indicated by a LOW read enable signal RE and a desire to perform a write operation is indicated by a LOW write enable signal WE.” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Yang into the device and/or method of claim 2 as modified above in a manner such that the pre-charge assist signal would be activated in response to an indication for the memory device to execute a read or write operation, wherein a LOW read enable signal RE would serve as the indication to perform the read operation, and a LOW write enable signal WE would serve as the indication to perform the write operation is associated with a write enable signal. The motivation to do so would have been to provide a signal to indicate the desire to execute the read or write operation based on which the pre-charging of the bit lines would be performed. Regarding claim 8: Claim 2 of the reference as modified by Hong and Goetz already teaches that a pre-charge of bit lines is performed in preparation for a data reading or writing operation (see [0002] of Goetz) ; however, does not specifically teach the pre-charge assist signal is associated with a write enable signal. Yang ([0055]) states “a desire to perform a read operation is indicated by a LOW read enable signal RE and a desire to perform a write operation is indicated by a LOW write enable signal WE.” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Yang into the device and/or method of claim 2 as modified above in a manner such that the pre-charge assist signal would be activated in response to an indication for the memory device to execute a read or write operation, wherein a LOW read enable signal RE would serve as the indication to perform the read operation, and a LOW write enable signal WE would serve as the indication to perform the write operation is associated with a write enable signal. The motivation to do so would have been to provide a signal to indicate the desire to execute the read or write operation based on which the pre-charging of the bit lines would be performed . 08-36 AIA Claim s 9, 10, 13, and 16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 11 of U.S. Patent No. US 12,080,342 (hereinafter “reference patent”) in view of Goetz (US 2008/0123448) and Huber et al. (US 2017/0162255) . Regarding claim 9: Claim 11 of the reference patent teaches a memory device, comprising: a first plurality of memory cells arranged in a first column of a memory cell array (identical to language of claim 11 of the reference patent; hence, anticipated) ; a first bit line connected to each of the first plurality memory cells (identical to language of claim 11 of the reference patent; hence, anticipated) ; a first bit line bar connected to each of the first plurality of memory cells (identical to language of claim 11 of the reference patent; hence, anticipated) ; a pre-charge circuit connected to both the first bit line and the first bit line bar, wherein the pre-charge circuit pre-charges each of the first bit line and the first bit line bar from a near end (identical to language of claim 11 of the reference patent; hence, anticipated) ; and a second circuit (a pre-charge assist circuit) connected to both the first bit line and the first bit line bar, wherein the second circuit pre-charges each of the first bit line and the second bit line from a second end (a far end) . Claim 11 of the reference patent does not specifically teach: at least one transistor connected to both the pre-charge circuit and a far end of each of the first bit line and the first bit line bar, wherein the at least one transistor pre-charges each of the first bit line and the first bit line bar from the second end. Goetz (FIG. 2; [0002-0004, 0019-0022]) teaches concurrently pre-charging a bit line of a memory array from both ends, wherein a PMOS transistor (224 1 ) is connected at the far end or top end of a bit line and is controlled by the same control signal as the pre-charge circuit at the near or bottom end. Goetz discloses that pre-charging the bit line from both ends reduces the pre-charging time. Huber (FIG. 1A; [0027-0029]) teaches a conventional power header/bit line precharge circuit, wherein a header transistor (102) is connected between bit line precharging transistors 103 and supply voltage 101. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Huber (conventional pre-charge circuit of FIG. 1A of Huber; [0027-0029]) into the device and/or method of claim 11 of the reference patent in a manner such that a circuit like 100 of Huber (from FIG. 1A of Huber) would be part of the pre-charge assist circuit and would be arranged at the top of the memory cell array, the pre-charge assist circuit would then comprise at least one transistor (PMOS header transistor 102 from FIG. 1A of Huber) with its source terminal connected to supply voltage VDD and its gate terminal connected to a power enable signal, and PMOS transistors 103 from Huber controlled by a pre-charge signal that would also control the pre-charge circuit (like that taught by Goetz), wherein and the pre-charge assist circuit would pre-charge the bit lines from the top ends (far ends) of the bit lines while the pre-charge circuit would pre-charge the bit lines from the bottom ends (near ends) of the bit lines. Hence, the pre-charge assist circuit would comprise at least one transistor (PMOS 102 from FIG. 1A of Huber) connected to both the pre-charge circuit (via the control signal) and a far end of each of the first bit line and the first bit line bar, wherein the at least one transistor pre-charges each of the first bit line and the first bit line bar from the second end. The motivation to do so would have been to incorporate a conventional bit line precharge circuit as exemplified by Huber to enjoy the benefits disclosed by Goetz such to precharge bit lines from both ends, while having a control signal in common, to reduce the pre-charge time of the memory array ([0019-0022] of Goetz) in preparation for a data reading operation or a data writing operation (see [0002] of Goetz) . Regarding claim 10: Claim 12 of the reference patent teaches the subject matter of this claim. Regarding claim 13: Claims 13 of the reference patent teaches the subject matter of this claim. Regarding claim 16: Claim 11 of the reference patent as modified above teaches the at least one transistor comprises a PMOS transistor (see modification above; PMOS header transistor 102 from FIG. 1A of Huber). Claims 11-12 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 12 of the reference patent ( US 12,080,342) as modified by Goetz (US 2008/0123448) and Huber et al. (US 2017/0162255) in view of Yang et al. (US 2014/0269021; hereinafter “Yang”) . Regarding claim 11: In so far as definite, Claim 12 of the reference as modified above already teaches that a pre-charge of bit lines is performed in preparation for a data reading or writing operation (see [0002] of Goetz) ; however, does not specifically teach the pre-charge assist signal or pre-charge signal is associated with a read enable signal. Yang ([0055]) states “a desire to perform a read operation is indicated by a LOW read enable signal RE and a desire to perform a write operation is indicated by a LOW write enable signal WE.” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Yang into the device and/or method of claim 12 of the reference patent as modified above in a manner such that the pre-charge assist signal would be activated in response to an indication for the memory device to execute a read or write operation, wherein a LOW read enable signal RE would serve as the indication to perform the read operation, and a LOW write enable signal WE would serve as the indication to perform the write operation is associated with a write enable signal. The motivation to do so would have been to provide a signal to indicate the desire to execute the read or write operation based on which the pre-charging of the bit lines would be performed. Regarding claim 12: In so far as definite, Claim 12 of the reference as modified above already teaches that a pre-charge of bit lines is performed in preparation for a data reading or writing operation (see [0002] of Goetz) ; however, does not specifically teach the pre-charge assist signal or pre-charge signal is associated with a write enable signal. Yang ([0055]) states “a desire to perform a read operation is indicated by a LOW read enable signal RE and a desire to perform a write operation is indicated by a LOW write enable signal WE.” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Yang into the device and/or method of claim 12 as modified above in a manner such that the pre-charge assist signal would be activated in response to an indication for the memory device to execute a read or write operation, wherein a LOW read enable signal RE would serve as the indication to perform the read operation, and a LOW write enable signal WE would serve as the indication to perform the write operation is associated with a write enable signal. The motivation to do so would have been to provide a signal to indicate the desire to execute the read or write operation based on which the pre-charging of the bit lines would be performed. Claims 14-15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 11 of the reference patent ( US 12,080,342) as modified by Goetz (US 2008/0123448) and Huber et al. (US 2017/0162255) in view of Rajendra et al. (US 2020/0076412; hereinafter “Rajendra”) . Regarding claim 14: Claim 11 of the reference patent as modified above does not specifically teach a number of the at least one transistor is dependent on a number of the first plurality of memory cells. Rajendra ([0090-0091]) teaches connecting transistors in parallel has the effect of increasing the effective gate width of the circuit, which in then increases the drive strength of the circuit, accordingly, a parallel combination of transistors has a larger effective gate width and drive strength compared to any single one of the transistors. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Rajendra into claim 11 of the reference patent as modified above in a manner such that the header transistor would comprise a plurality of transistors connected in paralel, wherein a source/drain of each of the plurality of transistors would be connected to the supply voltage VDD, wherein a drain/source of each of the plurality of transistors would be connected to both the first bit line and the second bit line, and wherein a gate of each of the plurality of transistors would be operable to receive the power on enable signal. Furthermore, the number of transistors connected in parallel would be determined based on the resistance and capacitive load (RC load) of a BL, which inherently depends on a number of the first plurality of memory cells (the number of memory cells per column of the memory array) since the transistors connected in parallel would need to have a drive strength sufficient to drive the RC load of each column of memory cells and Rajendra teaches the drive strength depends on the number of transistors connected in parallel. The motivation to do so would have been to increase the drive strength of the header transistor by replacing it with a plurality of transistors connected in parallel, wherein the drive strength would be sufficient to drive an RC load inherently provided by each column of the memory cell array and inherently depending on a number of the first plurality of memory cells (the number of memory cells per column of the memory array). Sizing transistors and determining how many to connect in parallel to sufficiently drive RC loads and meet timing requirements is within ordinary skill in the art of a circuit designer. Regarding claim 15: Claim 11 of the reference patent as modified above does not specifically teach the at least one transistor comprises two or more transistors are connected in parallel Rajendra ([0090-0091]) teaches connecting transistors in parallel has the effect of increasing the effective gate width of the circuit, which in then increases the drive strength of the circuit, accordingly, a parallel combination of transistors has a larger effective gate width and drive strength compared to any single one of the transistors. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Rajendra into the device and/or method of claim 11 of the reference patent as modified above in a manner such that the header transistor would comprise a plurality of transistors connected in parallel, wherein a source/drain of each of the plurality of transistors would be connected to the supply voltage VDD, wherein a drain/source of each of the plurality of transistors would be connected to both the first bit line and the second bit line, and wherein a gate of each of the plurality of transistors would be operable to receive the power on enable signal. Furthermore, the number of transistors connected in parallel would be determined based on the resistance and capacitive load (RC load) of a BL, which inherently depends on a number of the first plurality of memory cells (the number of memory cells per column of the memory array) since the transistors connected in parallel would need to have a drive strength sufficient to drive the RC load of each column of memory cells and Rajendra teaches the drive strength depends on the number of transistors connected in parallel. The motivation to do so would have been to increase the drive strength of the header transistor by replacing it with a plurality of transistors connected in parallel, wherein the drive strength would be sufficient to drive an RC load inherently provided by each column of the memory cell array and inherently depending on a number of the first plurality of memory cells (the number of memory cells per column of the memory array). Sizing transistors and determining how many to connect in parallel to sufficiently drive RC loads and meet timing requirements is within ordinary skill in the art of a circuit designer . Claim Rejections - 35 USC § 112 07-30-01 AIA The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. 07-31-01 Claims 2, 3, 5-8, and 10-15 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Regarding claim 2: The claim claims a transistor (“the transistor”) being connected to both the first bit line and the second bit line but the only figures illustrating this limitation are Figure 1 and Figure 4, which are devices expected, by one of ordinary skill in the art, to NOT work due to hard wired shorts (all of the bit lines, including complementary pairs, are explicitly permanently shorted together across all of the columns of the memory array) explicitly drawn in the respective figure. Hence, the subject matter was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claims 3, 7, and 8 depend on claim 2. Regarding claim 3: This claim claims “the transistor is switched on in response to the pre-charge assist signal rising to a pre-determined value connecting both the first bit line and the second bit line to the supply voltage” but such subject matter is NOT found in the drawings and/or specification. Regarding claim 5: This claim claims “the pre-charge assist circuit comprises a plurality of transistors connected in parallel to each other” but the only figure illustrating this limitation is Figure 4, which is a device expected, by one of ordinary skill in the art, to NOT work due to hard wired shorts (all of the bit lines, including complementary pairs, are explicitly permanently shorted together across all of the columns of the memory array) explicitly drawn in the figure. Hence, the subject matter was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claims 6 depends on claim 5. Regarding claim 10: For reasons similar to that of claim 2. Claim 13 also has the problem. Claims 11-13 depend on claim 10. Regarding each of claim 14 and 15: These claims correspond to Figure 4, which is a device expected, by one of ordinary skill in the art, to NOT work due to hard wired shorts (all of the bit lines, including complementary pairs, are explicitly permanently shorted together across all of the columns of the memory array) explicitly drawn in the figure. Hence, the subject matter was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 2-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 2: Each of the two instances of “the transistor” lacks sufficient antecedent basis. Claims 3, 7, and 8 depend on claim 2. Regarding claim 3: The limitation “the transistor” lacks sufficient antecedent basis. Regarding claim 4: The limitation “the transistor” lacks sufficient antecedent basis. Regarding claim 5: The limitation “the pre-charge assist circuit” lacks sufficient antecedent basis. Claim 6 depends on claim 5. Regarding claim 9: The limitation “the second end” lacks sufficient antecedent basis. Claims 10-16 depend on claim 9. Regarding each of claims 11 and 12: The limitation “the pre-charge assist signal” lacks sufficient antecedent basis. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-103 AIA The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim (s) 1, 2, 4, and 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong (US 20200075089) in view of Goetz et al. (US 2008/0123448; hereinafter “Goetz”) . Regarding claim 1: Hong (FIG. 1, FIG. 3 and FIG. 4; [0018-0030]) teaches a memory device, comprising: a memory cell array (110 in FIG. 1, cells 200 in FIG. 2 or FIG. 3 are in the array 110, the array 110 is also in FIG. 4) comprising a plurality of memory cells (cell 200) arranged in a matrix of a plurality of rows (each row of cells of the array corresponds to a WL of WL<0:m-1> in FIG. 3) and a plurality of columns (each column corresponds to a complementary bit line pair BL and BLB from among n bit line pairs in FIG. 3) , wherein each of the plurality of columns comprises a first plurality (m) of memory cells connected to a first bit line (BL) and a second bit line (BLB) ; and a pre-charge circuit (102 in FIG. 1 or FIG. 3 or FIG. 4) connected to the memory cell array, wherein the pre-charge circuit pre-charges each of the first bit line and the second bit line from a first end (bottom end, which is the end that has Sense Amplifier/Write Driver circuit 112 arranged at) . Hong does not specifically teach the following: at least one transistor connected between pre-charge circuit and a second end of each of the first bit line and the second bit line, wherein the at least one transistor pre-charges each of the first bit line and the second bit line from the second end. Goetz (FIG. 2; [0002-0004, 0019-0022]) teaches concurrently pre-charging a bit line of a memory array from both ends, wherein a PMOS transistor (224 1 ) is connected at the far end or top end of a bit line and is controlled by the same control signal as the pre-charge circuit at the near or bottom end. Goetz discloses that pre-charging the bit line from both ends reduces the pre-charging time. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Goetz into the device and/or method of Hong in a manner such that PMOS transistors would be arranged at the top of the memory array 110, wherein each of the PMOS transistors would have an upper source terminal connected to a pre-charge voltage VDD (VDD is known to refer to a high level supply voltage as exemplified in [0020, 0024) , a gate connected to control signal BLPCH after BLPCH traverses horizontally through the precharge circuit 102 as seen in FIG. 4 of Hong, and a lower drain terminal directly connected to a respective bit line of the array (BL or BLB; each bit line, regardless of whether it is a BL or BLB would pre-charged via a corresponding PMOS transistor of the PMOS transistors being added) to pre-charge each bit line from the top end in response to the bit line pre-charge control signal BLPCH such that each bit line would be pre-charged from the top end by the PMOS transistors while the bit line precharge device 102 pre-charges the same bit lines from the lower end. Note that the at least one transistor (the PMOS transistors at the top of the memory array) are considered to be connected between pre-charge circuit 102 and a second end (top end) of each of the first bit line and the second bit line because the control signal BLPCH transits through 102 and then to the control gates of the at least one PMOS transistor in the same fashion as that illustrated in Applicant’s figures Figure 1, Figure 4, and Figure 5. The motivation to do so would have been to enjoy the benefits disclosed by Goetz such as reducing the pre-charge time of the memory array ([0019-0022] of Goetz) in preparation for a data reading operation or a data writing operation (see [0002] of Goetz) . Regarding claim 2: Hong as modified above teaches the memory device of claim 1, wherein a source/drain of the transistor [the at least one transistor] is connected to a supply voltage (the source of each PMOS transistor is connected to VDD) , wherein a drain/source of the transistor [the at least one transistor] is connected to both the first bit line and the second bit line at the second end (some of the PMOS transistors have their drain directly connected to a true bit line BL and others have their drain directly connected to a complement bit line BLB; hence, the at least one transistor is connected to both the first bit line and the second bit line at the second end ) , and wherein a gate of the transistor is operable to receive a pre-charge assist signal (BLPCH; [0028] of Hong) . Regarding claim 4: Hong as modified above teaches the memory device of claim 1, wherein the transistor comprises one the following: a p-channel Metal Oxide Semiconductor transistor (PMOS) (the transistor symbol for 224 1 in FIG. 2 of Goetz is recognized by one of ordinary skill in the art to be the standard symbol of a p-channel CMOS or PMOS transistor) , a n-channel Metal Oxide Semiconductor transistor (NMOS), a Complementary Metal Oxide Semiconductor (CMOS), and a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). Regarding claim 17: Hong (FIG. 1, FIG. 3 and FIG. 4; [0018-0030]) teaches a method of pre-charging bit lines of a memory device, the method comprising: providing a first plurality of memory cells arranged in a first column of a memory cell array (m memory cells in a left most column of array 110 as illustrated in FIG. 3, for example) ; providing a first bit line (BL<0>) connected to each of the first plurality memory cells; providing a first complementary bit line (BLB<0>) connected to each of the first plurality of memory cells; and pre-charging both the first bit line and the first complementary bit line from a near end (bottom end) through a pre-charge circuit (102 in FIG. 3) , wherein the pre-charge circuit is connected to the near end of each of the first bit line and the first complementary bit line (bottom end, which is the end that has Sense Amplifier/Write Driver circuit 112 arranged at) . Hong does not specifically teach the following: pre-charging both the first bit line and the first complementary bit line from a far end through at least one transistor, wherein the at least one transistor is connected to the pre-charge circuit and the far end of each of the first bit line and the first complementary bit line. Goetz (FIG. 2; [0002-0004, 0019-0022]) teaches concurrently pre-charging a bit line of a memory array from both ends, wherein a PMOS transistor (224 1 ) is connected at the far end or top end of a bit line and is controlled by the same control signal as the pre-charge circuit at the near or bottom end. Goetz discloses that pre-charging the bit line from both ends reduces the pre-charging time. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Goetz into the device and/or method of Hong in a manner such that PMOS transistors would be arranged at the top of the memory array 110, wherein each of the PMOS transistors would have an upper source terminal connected to a pre-charge voltage VDD (VDD is known to refer to a high level supply voltage as exemplified in [0020, 0024) , a gate connected to control signal BLPCH after BLPCH traverses horizontally through the precharge circuit 102 as seen in FIG. 4 of Hong, and a lower drain terminal directly connected to a respective bit line of the array (BL or BLB; each bit line, regardless of whether it is a BL or BLB would pre-charged via a corresponding PMOS transistor of the PMOS transistors being added) to pre-charge each bit line from the top end in response to the bit line pre-charge control signal BLPCH such that each bit line would be pre-charged from the top end by the PMOS transistors while the bit line precharge device 102 pre-charges the same bit lines from the lower end. Note that the at least one transistor (the PMOS transistors at the top of the memory array) are considered to be connected between pre-charge circuit 102 and a second end (top end) of each of the first bit line and the second bit line because the control signal BLPCH transits through 102 and then to the control gates of the at least one PMOS transistor in the same fashion as that illustrated in Applicant’s figures Figure 1, Figure 4, and Figure 5. The motivation to do so would have been to enjoy the benefits disclosed by Goetz such as reducing the pre-charge time of the memory array ([0019-0022] of Goetz) in preparation for a data reading operation or a data writing operation (see [0002] of Goetz) . Regarding claim 18: Hong as modified above teaches the method of claim 17, wherein pre-charging both the first bit line and the first complementary bit line from the far end through the at least one transistor comprises pre-charging both the first bit line and the first complementary bit line from the far end through the at least one transistor substantially simultaneously with pre-charging both the first bit line and the first complementary bit line from the near end through the pre-charge circuit (Goetz: FIG. 2; [0002-0004, 0019-0022]) . Regarding claim 19: Hong as modified above teaches the method of claim 17, wherein pre-charging both the first bit line and the first complementary bit line from the far end through the at least one transistor comprises pre-charging both the first bit line and the first complementary bit line from the far end through the at least one transistor in response to receiving a pre-charge assist signal (see the modification above, wherein BLPCH signal transits across bit line precharge device 102 in FIG. 4 of Hong, and then goes up to drive the control gates of the PMOS transistors 224 1 from FIG. 2 of Goetz) . Regarding claim 20: Hong as modified above teaches the method of claim 19, wherein receiving the pre-charge assist signal comprises receiving the pre-charge assist signal from the pre-charge circuit (since as explained above in the mdofication, the BLPCH signal transits across the precharge circuit 102 as illustrated in FIG. 4 of Hong, and then goes up to drive the gates of the added PMOS transistors at the top end of the memory array from Goetz) . 07-21-aia AIA Claim (s) 5-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong (US 20200075089) as modified by Goetz (US 2008/0123448) in view of Huber et al. (US 2017/0162255) and Rajendra et al. (US 2020/0076412) . Regarding claims 5-6: Hong as modified above does not specifically teach the memory device of claim 1, wherein the pre-charge assist circuit [the at least one transistor] comprises a transistor, wherein a source/drain of each of the transistor is connected to a supply voltage, wherein a drain/source of the transistor is connected to both the first bit line and the second bit line, and wherein a gate of the transistor is operable to receive [the] pre-charge assist signal. Huber (FIG. 1A; [0027-0029]) teaches a conventional power header/bit line precharge circuit, wherein a header transistor (102) is connected between bit line precharging transistors 103 and supply voltage 101. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Huber into the device and/or method of Hong as modified above in a manner such that a header transistor like that of Huber (102) would be connected between the PMOS transistors from Goetz and the supply voltage VDD. Note that the power enable signal driving the gate of the header transistors would be included in the pre-charge assist signal. The motivation to do so would have been to use a header precharge transistor so precharge the bit lines since it was already known in the art to be a conventional type circuit suitable for pre-charging a plurality of bit lines as exemplified by Huber. Hong as modified by Goetz and Huber, does not specifically teach the header transistor comprises a plurality of transistors, wherein a source/drain of each of the plurality of transistors is connected to the supply voltage, wherein a drain/source of each of the plurality of transistors is connected to both the first bit line and the second bit line, and wherein a gate of each of the plurality of transistors is operable to receive the pre-charge assist signal, and (regarding claim 6) a number of the plurality of transistors is determined based on a number of the first plurality of memory cell. Rajendra ([0090-0091]) teaches connecting transistors in parallel has the effect of increasing the effective gate width of the circuit, which in tern increases the drive strength of the circuit, accordingly, a parallel combination of transistors has a larger effective gate width and drive strength compared to any single one of the transistors. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Rajendra into the device and/or method of Hong as modified above in a manner such that the header transistor would comprise a plurality of transistors, wherein a source/drain of each of the plurality of transistors would be connected to the supply voltage VDD, wherein a drain/source of each of the plurality of transistors would be connected to both the first bit line and the second bit line, and wherein a gate of each of the plurality of transistors would be operable to receive the pre-charge assist signal (a power enable signal included in the pre-charge assist signal). Furthermore, the number of transistors connected in parallel would be determined based on the resistance and capacitive load (RC load) of a BL, which inherently depends on a number of the first plurality of memory cells (the number of memory cells per column of the memory array) since the transistors connected in parallel would need to have a drive strength sufficient to drive the RC load of each column of memory cells and Rajendra teaches the drive strength depends on the number of transistors connected in parallel. The motivation to do so would have been to increase the drive strength of the header transistor by replacing it with a plurality of transistors connected in parallel, wherein the drive strength would be sufficient to drive an RC load inherently provided by each column of the memory cell array and inherently depending on a number of the first plurality of memory cells (the number of memory cells per column of the memory array). Sizing transistors and determining how many to connect in parallel to sufficiently drive RC loads and meet timing requirements is within ordinary skill in the art of a circuit designer . 07-21-aia AIA Claim (s) 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong (US 20200075089) as modified by Goetz (US 2008/0123448) in view of Yang et al. (US 2014/0269021; hereinafter “Yang”) . Regarding claim 7: Hong as modified above already teaches that a pre-charge of bit lines is performed in preparation for a data reading or writing operation (see [0002] of Goetz) . Hong does not specifically teach the pre-charge assist signal is associated with a read enable signal. Yang ([0055]) states “a desire to perform a read operation is indicated by a LOW read enable signal RE and a desire to perform a write operation is indicated by a LOW write enable signal WE.” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Yang into the device and/or method of Hong as modified above in a manner such that the pre-charge assist signal would be activated in response to an indication for the memory device to execute a read or write operation, wherein a LOW read enable signal RE would serve as the indication to perform the read operation, and a LOW write enable signal WE would serve as the indication to perform the write operation is associated with a write enable signal. The motivation to do so would have been to provide a signal to indicate the desire to execute the read or write operation based on which the pre-charging of the bit lines would be performed. Regarding claim 8: Hong as modified above already teaches that a pre-charge of bit lines is performed in preparation for a data reading or writing operation (see [0002] of Goetz) . Hong does not specifically teach the pre-charge assist signal is associated with a write enable signal. Yang ([0055]) states “a desire to perform a read operation is indicated by a LOW read enable signal RE and a desire to perform a write operation is indicated by a LOW write enable signal WE.” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Yang into the device and/or method of Hong as modified above in a manner such that the pre-charge assist signal would be activated in response to an indication for the memory device to execute a read or write operation, wherein a LOW read enable signal RE would serve as the indication to perform the read operation, and a LOW write enable signal WE would serve as the indication to perform the write operation is associated with a write enable signal. The motivation to do so would have been to provide a signal to indicate the desire to execute the read or write operation based on which the pre-charging of the bit lines would be performed . 07-21-aia AIA Claim (s) 9, 10, 13, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong (US 20200075089) in view of Goetz (US 2008/0123448) and Huber et al. (US 2017/0162255) . Regarding claim 9: Hong (FIG. 1, FIG. 3 and FIG. 4; [0018-0030]) teaches a memory device, comprising: a first plurality of memory cells arranged in a first column of a memory cell array (m memory cells in a left most column of array 110 as illustrated in FIG. 3, for example) ; a first bit line (BL<0>) connected to each of the first plurality memory cells; a first bit line bar (BLB<0>) connected to each of the first plurality of memory cells; a pre-charge circuit (102) connected to both the first bit line and the first bit line bar, wherein the pre-charge circuit pre-charges each of the first bit line and the first bit line bar from a near end (bottom end, which is the end that has Sense Amplifier/Write Driver circuit 112 arranged at) . Hong does not specifically teach the following: at least one transistor connected to both the pre-charge circuit and a far end of each of the first bit line and the first bit line bar, wherein the at least one transistor pre-charges each of the first bit line and the first bit line bar from the second end. Goetz (FIG. 2; [0002-0004, 0019-0022]) teaches concurrently pre-charging a bit line of a memory array from both ends, wherein a PMOS transistor (224 1 ) is connected at the far end or top end of a bit line and is controlled by the same control signal as the pre-charge circuit at the near or bottom end. Goetz discloses that pre-charging the bit line from both ends reduces the pre-charging time. Huber (FIG. 1A; [0027-0029]) teaches a conventional power header/bit line precharge circuit, wherein a header transistor (102) is connected between bit line precharging transistors 103 and supply voltage 101. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Huber (conventional precharge circuit of FIG. 1A of Huber; [0027-0029]) into the device and/or method of Hong as modified above in a manner such that a precharge circuit like 100 of Huber would be arranged at the top of the memory array 110 of Hong, the precharge circuit would comprise at least one transistor (PMOS header transistor 102 from FIG. 1A of Huber) with its source terminal connected to supply voltage VDD and its gate terminal connected to a power enable signal, which may be driven with timing similar to that of the BLPCH signal of Hong, the transistors 103 of the precharge circuit would be controlled by signal BLPCH of Hong, and the precharge circuit would precharge the bit liens from the top ends of the bit lines while circuit 102 of Hong would precharge the bit lines from the bottom ends of the bit lines. The motivation to do so would have been to incorporate a conventional bit line precharge circuit as exemplified by Huber to enjoy the benefits disclosed by Goetz such to precharge bit lines from both ends to reduce the pre-charge time of the memory array ([0019-0022] of Goetz) in preparation for a data reading operation or a data writing operation (see [0002] of Goetz) . Regarding claim 10: Hong as modified above teaches the memory device of claim 9, wherein a source/drain of each of the at least one transistor (header PMOS transistor 102) is connected to a supply voltage (the source of header PMOS transistor is connected to VDD) , wherein a drain/source of each of the at least one transistor is connected to the both the first bit line and the first bit line bar (some of the PMOS transistors 103 from Huber have their drain directly connected to a true bit line BL and others have their drain directly connected to a complement bit line BLB; hence, the at least one transistor is connected to both the first bit line and the second bit line at the second end or top end) , and wherein a gate of the at least one transistor (102 from Huber) is operable to receive a pre-charge signal (power enable signal from Huber) . Regarding claim 13: Hong as modified above teaches the at least one transistor is operative to connect both the first bit line and the first bit line bar to the supply voltage in response to the pre-charge signal attaining a predetermined logic value (since the transistors 102 from Huber is recognized to be the standard symbol for a PMOS transistor then the transistor inherently turns ON upon the pre-charge signal or power on enable signal attaining the predetermined logic value of zero or logic LOW) . Regarding claim 16: Hong as modified above teaches the at least one transistor comprises one the following: a p-channel Metal Oxide Semiconductor transistor (PMOS) (the transistor symbol for 102 in FIG. 1A of Huber is recognized by one of ordinary skill in the art to be the standard symbol of a p-channel CMOS or PMOS transistor) , a n-channel Metal Oxide Semiconductor transistor (NMOS), a Complementary Metal Oxide Semiconductor (CMOS), and a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) . 07-21-aia AIA Claim (s) 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong (US 20200075089) as modified by Goetz (US 2008/0123448) and Huber et al. (US 2017/0162255) in view of Yang et al. (US 2014/0269021; hereinafter “Yang”) . Regarding claim 11: Hong as modified above already teaches that a pre-charge of bit lines is performed in preparation for a data reading or writing operation (see [0002] of Goetz) . Hong as modified above does not specifically teach the pre-charge assist signal is associated with a read enable signal. Yang ([0055]) states “a desire to perform a read operation is indicated by a LOW read enable signal RE and a desire to perform a write operation is indicated by a LOW write enable signal WE.” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Yang into the device and/or method of Hong as modified above in a manner such that the pre-charge assist signal would be activated in response to an indication for the memory device to execute a read or write operation, wherein a LOW read enable signal RE would serve as the indication to perform the read operation, and a LOW write enable signal WE would serve as the indication to perform the write operation is associated with a write enable signal. The motivation to do so would have been to provide a signal to indicate the desire to execute the read or write operation based on which the pre-charging of the bit lines would be performed. Regarding claim 12: Hong as modified above already teaches that a pre-charge of bit lines is performed in preparation for a data reading or writing operation (see [0002] of Goetz) . Hong does not specifically teach the pre-charge assist signal is associated with a write enable signal. Yang ([0055]) states “a desire to perform a read operation is indicated by a LOW read enable signal RE and a desire to perform a write operation is indicated by a LOW write enable signal WE.” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Yang into the device and/or method of Hong as modified above in a manner such that the pre-charge assist signal would be activated in response to an indication for the memory device to execute a read or write operation, wherein a LOW read enable signal RE would serve as the indication to perform the read operation, and a LOW write enable signal WE would serve as the indication to perform the write operation is associated with a write enable signal. The motivation to do so would have been to provide a signal to indicate the desire to execute the read or write operation based on which the pre-charging of the bit lines would be performed . 07-21-aia AIA Claim (s) 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong (US 20200075089) as modified by Goetz (US 2008/0123448) and Huber et al. (US 2017/0162255) in view of Rajendra et al. (US 2020/0076412) . Regarding claim 14: Hong as modified above does not specifically teach a number of the at least one transistor is dependent on a number of the first plurality of memory cells. Rajendra ([0090-0091]) teaches connecting transistors in parallel has the effect of increasing the effective gate width of the circuit, which in then increases the drive strength of the circuit, accordingly, a parallel combination of transistors has a larger effective gate width and drive strength compared to any single one of the transistors. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Rajendra into the device and/or method of Hong as modified above in a manner such that the header transistor would comprise a plurality of transistors, wherein a source/drain of each of the plurality of transistors would be connected to the supply voltage VDD, wherein a drain/source of each of the plurality of transistors would be connected to both the first bit line and the second bit line, and wherein a gate of each of the plurality of transistors would be operable to receive the power on enable signal. Furthermore, the number of transistors connected in parallel would be determined based on the resistance and capacitive load (RC load) of a BL, which inherently depends on a number of the first plurality of memory cells (the number of memory cells per column of the memory array) since the transistors connected in parallel would need to have a drive strength sufficient to drive the RC load of each column of memory cells and Rajendra teaches the drive strength depends on the number of transistors connected in parallel. The motivation to do so would have been to increase the drive strength of the header transistor by replacing it with a plurality of transistors connected in parallel, wherein the drive strength would be sufficient to drive an RC load inherently provided by each column of the memory cell array and inherently depending on a number of the first plurality of memory cells (the number of memory cells per column of the memory array). Sizing transistors and determining how many to connect in parallel to sufficiently drive RC loads and meet timing requirements is within ordinary skill in the art of a circuit designer. Regarding claim 15: Hong as modified above does not specifically teach the at least one transistor comprises two or more transistors are connected in parallel. Rajendra ([0090-0091]) teaches connecting transistors in parallel has the effect of increasing the effective gate width of the circuit, which in then increases the drive strength of the circuit, accordingly, a parallel combination of transistors has a larger effective gate width and drive strength compared to any single one of the transistors. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Rajendra into the device and/or method of Hong as modified above in a manner such that the header transistor would comprise a plurality of transistors, wherein a source/drain of each of the plurality of transistors would be connected to the supply voltage VDD, wherein a drain/source of each of the plurality of transistors would be connected to both the first bit line and the second bit line, and wherein a gate of each of the plurality of transistors would be operable to receive the power on enable signal. Furthermore, the number of transistors connected in parallel would be determined based on the resistance and capacitive load (RC load) of a BL, which inherently depends on a number of the first plurality of memory cells (the number of memory cells per column of the memory array) since the transistors connected in parallel would need to have a drive strength sufficient to drive the RC load of each column of memory cells and Rajendra teaches the drive strength depends on the number of transistors connected in parallel. The motivation to do so would have been to increase the drive strength of the header transistor by replacing it with a plurality of transistors connected in parallel, wherein the drive strength would be sufficient to drive an RC load inherently provided by each column of the memory cell array and inherently depending on a number of the first plurality of memory cells (the number of memory cells per column of the memory array). Sizing transistors and determining how many to connect in parallel to sufficiently drive RC loads and meet timing requirements is within ordinary skill in the art of a circuit designer. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY W RADKE whose telephone number is (571)270-1622. The examiner can normally be reached M-F 9-6 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. JAY W. RADKE Primary Examiner Art Unit 2827 /JAY W. RADKE/Primary Examiner, Art Unit 2827 Application/Control Number: 18/773,342 Page 2 Art Unit: 2827 Application/Control Number: 18/773,342 Page 3 Art Unit: 2827 Application/Control Number: 18/773,342 Page 4 Art Unit: 2827 Application/Control Number: 18/773,342 Page 5 Art Unit: 2827 Application/Control Number: 18/773,342 Page 6 Art Unit: 2827 Application/Control Number: 18/773,342 Page 7 Art Unit: 2827 Application/Control Number: 18/773,342 Page 8 Art Unit: 2827 Application/Control Number: 18/773,342 Page 9 Art Unit: 2827 Application/Control Number: 18/773,342 Page 10 Art Unit: 2827 Application/Control Number: 18/773,342 Page 11 Art Unit: 2827 Application/Control Number: 18/773,342 Page 12 Art Unit: 2827 Application/Control Number: 18/773,342 Page 13 Art Unit: 2827 Application/Control Number: 18/773,342 Page 14 Art Unit: 2827 Application/Control Number: 18/773,342 Page 15 Art Unit: 2827 Application/Control Number: 18/773,342 Page 17 Art Unit: 2827 Application/Control Number: 18/773,342 Page 18 Art Unit: 2827 Application/Control Number: 18/773,342 Page 19 Art Unit: 2827 Application/Control Number: 18/773,342 Page 20 Art Unit: 2827 Application/Control Number: 18/773,342 Page 21 Art Unit: 2827 Application/Control Number: 18/773,342 Page 22 Art Unit: 2827 Application/Control Number: 18/773,342 Page 23 Art Unit: 2827 Application/Control Number: 18/773,342 Page 24 Art Unit: 2827 Application/Control Number: 18/773,342 Page 25 Art Unit: 2827 Application/Control Number: 18/773,342 Page 26 Art Unit: 2827 Application/Control Number: 18/773,342 Page 27 Art Unit: 2827 Application/Control Number: 18/773,342 Page 28 Art Unit: 2827 Application/Control Number: 18/773,342 Page 29 Art Unit: 2827 Application/Control Number: 18/773,342 Page 30 Art Unit: 2827 Application/Control Number: 18/773,342 Page 31 Art Unit: 2827 Application/Control Number: 18/773,342 Page 32 Art Unit: 2827 Application/Control Number: 18/773,342 Page 33 Art Unit: 2827 Application/Control Number: 18/773,342 Page 34 Art Unit: 2827 Application/Control Number: 18/773,342 Page 35 Art Unit: 2827 Application/Control Number: 18/773,342 Page 36 Art Unit: 2827 Application/Control Number: 18/773,342 Page 37 Art Unit: 2827 Application/Control Number: 18/773,342 Page 38 Art Unit: 2827 Application/Control Number: 18/773,342 Page 39 Art Unit: 2827 Application/Control Number: 18/773,342 Page 40 Art Unit: 2827 Application/Control Number: 18/773,342 Page 41 Art Unit: 2827
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