DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 2 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation "the second connection pattern is different from the second connection pattern", and it seems to be a typographical error.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 9-12, 14-17, 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al. (PGPUB 20030052735), hereinafter as Kang.
Regarding claim 1, Kang teaches memory device comprising:
a first sub-block (Fig 13, block 32) comprising:
a first plurality of memory cells arranged in a first row and connected to a first bit line (Fig 13, cells, some are not shown in the figure, connected to BL4), and
a second plurality of memory cells arranged in a second row and connected to a first complementary bit line (Fig 13, cells connected to BL3), wherein the first plurality of memory cells of the first row and the second plurality of memory cells of the second row are connected to a plurality of word lines in a first connection pattern (Fig 13, pattern as in block 32), and wherein in the first connection pattern the first plurality of memory cells are connected to consecutive even numbered word lines of the plurality of word lines and the second plurality of memory cells are connected to consecutive odd numbered word lines of the plurality of word lines (Fig 13, cells connected to BL4 also connected to SW1 and SW5 (not shown), and cells connected to BL3 also connected to SW3 and SW7(not shown); SW1 and SW5 is equivalent as WL 1 and WL3 since SWL 2 and SWL4 are not functioned as WL for block 32, and SW3 and SW7 is equivalent as WL2 and WL4 since SWL 2/4/6 are not functioned as WL for block 32, it has been held that rearranging/renumbering parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.); and
a second sub-block (Fig 13, block 33) comprising:
a third plurality of memory cells arranged in a third row and connected to a second bit line (Fig 13, block 33 BL4), and
a fourth plurality of memory cells arranged in a fourth row and connected to a second complementary bit line (Fig 13, block 33, BL3), wherein the third plurality of memory cells of the third row and the fourth plurality of memory cells of the fourth row are connected to the plurality of word lines in a second connection pattern (Fig 13).
Regarding claim 3, Kang teaches the second connection pattern is complimentary to the connection pattern (Fig 13).
Regarding claim 9, Kang teaches a memory device comprising:
a first sub-block comprising:
a first bit line, a second bit line, a first plurality of memory cells connected to the first bit line, wherein each of the first plurality of memory cells are arranged in a first row, and a second plurality of memory cells connected to the second bit line, wherein each of the second plurality of memory cells are arranged in a second row;
a second sub-block comprising:
a third bit line, a fourth bit line, a third plurality of memory cells connected to the third bit line, wherein each of the third plurality of memory cells are arranged in a third row, and a fourth plurality of memory cells connected to the fourth bit line, wherein each of the fourth plurality of memory cells are arranged in a fourth row; and
a plurality of word lines, wherein:
the first plurality of memory cells and the second plurality of memory cells are connected to the plurality of word lines in a first pattern, the first pattern comprising the first plurality of memory cells being connected to consecutive even numbered word lines of the plurality of word lines and the second plurality of memory cells being connected to consecutive odd numbered word lines of the plurality of word lines, and
third plurality of memory cells and the fourth plurality of memory cells are connected the plurality of word lines in a second pattern (argument used in rejection of claim 1 applies).
Regarding claim 10, Kang teaches the second bit line is complementary to the first bit line, and wherein the fourth bit line is complementary to the third bit line (Fig 5).
Regarding claim 11, Kang teaches a first sense amplifier connected to both the first bit line and the second bit line; and a second sense amplifier connected to both the third bit line and the fourth bit line (Fig 5, others SA is not shown, but obvious present).
Regarding claim 12, Kang teaches the second pattern is different from the first pattern (Fig 13).
Regarding claim 14, Kang teaches a plurality of mini arrays each comprising a plurality of sub-blocks arranged according a connection pattern type (Fig 13).
Regarding claim 15, Kang teaches a plurality of mini arrays each comprising a plurality of sub-blocks of a same connection pattern type (Fig 13, regrouping is obvious to a person with ordinary skill in the art, In re Japikse, 86 USPQ 70).
Regarding claim 16, Kang teaches a method of connecting memory cells in a memory device, the method comprising: providing a memory device comprising a plurality of memory cells arranged in a plurality of rows; connecting a first plurality of memory cells arranged in a first row of the plurality of rows to a first bit line; connecting a second plurality of memory cells arranged in a second row of the plurality of rows to a first complementary bit line; connecting the first plurality of memory cells of the first row and the second plurality of memory cells of the second row to a plurality of word lines according to a first connection pattern, wherein connecting the first plurality of memory cells of the first row and the second plurality of memory cells of the second row to the plurality of word lines according to the first connection pattern comprises: connecting the first plurality of memory cells of the first row to consecutive even numbered word lines of the plurality of word lines; and connecting the second plurality of memory cells of the second row to consecutive odd numbered word lines of the plurality of word lines; connecting a third plurality of memory cells arranged in a third row of the plurality of rows to a second bit line; connecting a fourth plurality of memory cells arranged in a fourth row of the plurality of rows to a second complementary bit line; and connecting the third plurality of memory cells of the third row and the fourth plurality of memory cells of the fourth row to the plurality of word lines according to a second connection pattern (the argument used in rejection of claim 1 applies).
Regarding claim 17, Kang teaches the second connection pattern is different from the first connection pattern (Fig 13).
Regarding claim 19, Kang teaches generating a third connection pattern from the first connection pattern (repeat a pattern is obvious to a person with ordinary skill in the art, In re Japikse, 86 USPQ 70).
Regarding claim 20, Kang teaches re-arranging the plurality of rows based on a connection pattern type (repeat a pattern is obvious to a person with ordinary skill in the art, In re Japikse, 86 USPQ 70).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-20 of U.S. Patent No. 12087354. Although the claims at issue are not identical, they are not patentably distinct from each other, each claim of the instant application and matching claims of the related patent are list below in a table.
Instant app
12087354
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728
874
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Greyscale
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548
552
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Greyscale
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188
688
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Greyscale
Claim 2
Claim 1, 4
Claim 3
Claim 1, 4
Claim 7, 8
Claim 9, 19
Claim 9, 10
Claim 1, 4
Claim 11
Claim 9, 11
Claim 12
Claim 1, 2
Claim 13, 18
Claim 9
Claim 14
Claim 9, 13
Claim 15
Claim 9, 14
Claim 16, 17
Claim 1, 4
Claim 19
Claim 17
Claim 20
Claim 18
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIN HUANG whose telephone number is (571)270-5798. The examiner can normally be reached M-F 9-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571)272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MIN HUANG/Primary Examiner, Art Unit 2827