DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 07/15/24 was/were received by the Examiner before the issuance/mailing date of the first office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) has/have been considered (except for anything in foreign language non-accompanied by an English translation) by the Examiner.
Claim Objections
Claims 5-9 and 14-20 are objected to because of the following informalities:
claims 5, 8, 14 and 16 each recites “the insulating encapsulation”. This is incorrect and should be “the insulating encapsulation”.
Claim 17 recites “…, wherein in a cross-sectional area of each of the plurality of conductive joints is greater than a cross-sectional area of a respective one…” (emphasis added). The “in” should be deleted.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 10 and 13-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen (US 2016/0013144).
a. Re claim 10, Chen discloses a method of manufacturing a package structure, comprising: providing a first package 100 (less the bumps 126 on fig. 22 and related text; see remaining of disclosure for more details) having at least one first semiconductor die 102 ([0028]), a plurality of conductive pillars 122 ([0031]) next to and electrically connected to the at least one first semiconductor die, and a first insulating encapsulation 120 encapsulating the at least one first semiconductor die and the plurality of conductive pillars; removing a portion of the first insulating encapsulation to expose portions of the plurality of conductive pillars from the first insulating encapsulation (see fig. 23 and [0081]), wherein the exposed portions of the plurality of conductive pillars protrude out of the first insulating encapsulation; providing a second package 200 (figs. 24-25 and related text) having at least one second semiconductor die 204 and a plurality of conductive pads 208 electrically connected thereto ([0035]); and mounting the second package on the first package by a plurality of conductive connectors 206 ([0035]) disposed therebetween, the plurality of conductive connectors being sandwiched between and electrically connecting the first package and the second package.
b. Re claim 13, removing the portion of the first insulating encapsulation comprises performing an etching process ([0081]).
c. Re claim 14, Chen discloses method of claim 10, wherein prior to providing the first package, the method further comprises: forming the first package, comprising: providing the at least one first semiconductor die (explicit on fig. 21 and related text); disposing the plurality of conductive pillars 122 next to the at least one first semiconductor die (explicit on fig. 21 and related text); encapsulating the at least one first semiconductor die and the plurality of conductive pillars in the first insulating encapsulation (explicit on fig. 21 and related text); and forming a first redistribution circuit structure 112&114&124 ([0028]-[0024]) over the insulting encapsulation and electrically connecting the at least one first semiconductor die and the plurality of conductive pillars (explicit on fig. 21 and related text), wherein the second package is mounted to the first package at a side of the first package opposite to the first redistribution circuit structure (explicit on figs. 24-25).
d. Re claim 15, forming the first package further comprises at least one of: disposing a plurality of conductive terminals 126 (fig. 21 and related text) over the first redistribution circuit structure, wherein the first redistribution circuit structure is between the plurality of conductive terminals and the first insulating encapsulation; or disposing at least one semiconductor device over the first redistribution circuit structure laterally next to the plurality of conductive terminals, wherein the first redistribution circuit structure is between the at least one semiconductor device and the first insulating encapsulation.
e. Re claim 16, Chen discloses the method of claim 10, wherein prior to providing the second package, the method further comprises: forming the second package, comprising: forming a second redistribution circuit structure 202 (explicit on fig. 24); disposing the plurality of conductive pads over a first (bottom) side of the second redistribution circuit structure (explicit on fig. 24); disposing the at least one second semiconductor die over a second (top) side of the second redistribution circuit structure, the second side being opposite to the first side; encapsulating the least one second semiconductor die in a second insulating encapsulation (unlabeled but clearly shown on fig. 24 as encapsulating dies 204 and recognizable as such for a skilled in the art); disposing the plurality of conductive pillars next to the at least one first semiconductor die (explicit on fig. 21); encapsulating the at least one first semiconductor die and the plurality of conductive pillars in the insulating encapsulation (explicit on fig. 21); and forming a first redistribution circuit structure 112&114&124 ([0028]-[0024]) over the insulting encapsulation and electrically connecting the at least one first semiconductor die and the plurality of conductive pillars (explicit on fig. 21), wherein the second package is mounted to the first package by the plurality of conductive connectors disposed between the plurality of conductive pads of the second package and the plurality of conductive pillars of the first package (explicit on figs. 24-25).
Allowable Subject Matter
Claims 1-4 are allowed.
Claims 11-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 5-9 and 17-20 would be allowable assuming the objections stated above are overcome.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chen et al. (US 2016/0163566) and Prabhu et al. (US 2017/0141042) disclose a method of manufacturing a package similar to the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PENIEL M GUMEDZOE whose telephone number is (571)270-3041. The examiner can normally be reached M-F: 9:00AM - 5:30PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 5712707877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PENIEL M GUMEDZOE/Primary Examiner, Art Unit 2899
Prosecution Insights