DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to applicant’s Restriction/Election filed on 08/13/2026.
Currently claims 1-20 are pending in the application.
Election/Restrictions
Applicant's election without traverse of Group I, claims 1-9 and 19-20, in the reply filed on 08/13/2026 is acknowledged.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 07/15/2024 and 08/28/2026 were filed before the mailing date of the office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements were considered by the examiner.
Claim Rejections - 35 USC § 112 (b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-9 and 20 are rejected under 35 U.S.C. 112 (b), as being indefinite for failing to particularly pointing out and distinctly claim the subject matter which the inventor or a joint inventor, regard as their invention.
Regarding claim 1, the claim recites “a backside contact” (claim 1, line 2) and subsequently recites “the BDTI isolates a backside contact from a substrate” (claim 1, last line). It is unclear whether the second “backside contact” recalls the backside contact introduced in line 2 or introduces a different backside contact, rendering the claim indefinite. Clarification and/or correction are/is required. For the purpose of examination, the second recitation will be interpreted as “the backside contact.” Claims 2-9 are rejected by virtue of their dependency on claim 1.
Regarding claim 20, the claim recites “further comprising a backside contact, wherein the BDTI isolates a backside contact from a substrate.” It is unclear whether the second “backside contact” is the backside contact just introduced or a different one, rendering the claim indefinite. For the purpose of examination, the second recitation will be interpreted as “the backside contact.”
Regarding claims 5 and 7, claim 5 recites “through a frontside via and the backside via” (claim 5, last line) and claim 7 recites “a bottom surface of the backside via” (claim 7, line 2). There is insufficient antecedent basis for “the backside via” in these claims. Claims 5 and 7 depend directly from claim 1, which does not recite a backside via; a backside via is introduced only in claim 3, from which claims 5 and 7 do not depend. It is unclear which backside via is being recalled, rendering the claims indefinite. For the purpose of examination, “the backside via” will be interpreted as “a backside via of the backside contact.”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3 and 5-9 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0377945 A1 (Chuang) in view of US 2023/0317566 A1 (Fan).
Regarding claim 1, Chuang teaches, a semiconductor device (800; semiconductor feature; Fig. 12; [0021]), comprising:
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a backside contact (240; conductive structure; Fig. 13; [0020], [0022]);
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a shallow trench isolation (STI) (206; STI structure; Figs. 3, 13; [0011], [0022]); and
a backside dielectric trench isolation (BDTI) (224; dielectric filling layer, including first portion 262 and second portion 264; Figs. 9, 13; [0017] - [0018], [0022], formed from the backside in a trench disposed beneath the STI structure) below the STI (214; trench “disposed beneath a corresponding one of the STI structures 206”; Fig. 13; [0017]),
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wherein: a top surface (bottom surface in Fig. 7) of the BDTI (224) is connected to the STI (222; bottom wall portion defined by STI 206; Fig. 7; [0017] - [0018]) on a backside of a high voltage region of the semiconductor device (300; NLDMOS / BCD power device; Figs. 2-3; [0011], [0017]),
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a bottom surface of the BDTI (224) is connected to a backside interconnect (252/254/258; connecting feature/connecting pads/metal grid; Fig. 17; [0026]), and
the BDTI (264, part of 224; second portion of dielectric filling layer surrounding portion A1; Fig. 13; [0022], [0033]) isolates a backside contact (240) from a substrate (202; semiconductor substrate; Fig. 17; [0010], [0022]).
But Chuang fails to teach explicitly, the backside interconnect connected to the bottom surface of the BDTI is “a backside power interconnect.”
However, in analogous art, Fan teaches, a backside power delivery structure in which a power rail (250; power rail; Figs. 1F-1G; [0013], [0018]) at the backside of the device is connected, through a backside via (240; backside via; Figs. 1F-1G; [0018]) and a backside conductive feature (180; backside conductive feature; Fig. 1F; [0018], [0085]) formed in backside dielectric layers (160; first backside dielectric layer; Fig. 1F; [0018], [0085]), to a via extending through the STI to a source/drain contact.
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Chuang and Fan before him/her, to modify the teachings of a semiconductor device including a backside interconnect as taught by Chuang and to include the teachings of backside interconnect being a backside power delivery structure as taught by Fan because delivering power from the backside improves frontside signal-routing flexibility and permits wider power rails that reduce resistance and increase power efficiency (Fan, [0012] - [0013]). Absent this teaching in Chuang, a person with ordinary skill in the art would be motivated to reach out to Fan while forming a semiconductor device of Chuang.
Regarding claim 3, the combination of Chuang and Fan teaches, the semiconductor device of claim 1, wherein: the backside contact includes a backside via connected to a frontside via - Chuang teaches the conductive structure having a first (lower) portion A1 and a second (upper) portion A2 connected together (A1/A2; first and second portions of conductive structure 240; Chuang Fig. 13; [0022]), the second portion extending through the STI structure and the dielectric structure on the front side to the first metal layer (502; first metal layer; Chuang Fig. 13; [0022]); to the extent the claim requires discrete via elements, Fan teaches a frontside power via (150; power via; Fan Figs. 1B, 1F; [0013], [0018]) connected to a backside conductive feature and backside via, and forming an integral conductor as separate connected parts is an obvious design choice (MPEP 2144.04(V)(C));
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the STI covers lower portions of sidewalls of the frontside via - Chuang’s second portion A2 is surrounded by the STI structure (lower, adjacent A1) (206; STI structure; Chuang Fig. 13; [0022]) and by the dielectric structure (upper) (204; dielectric structure; Chuang Fig. 13; [0022]); and
the BDTI covers sidewalls of the backside via - Chuang’s second portion of the dielectric filling layer surrounds first portion A1 (264; second portion of dielectric filling layer; Chuang Fig. 13; [0022]). Chuang teaches the STI/BDTI arrangement; Fan teaches the discrete frontside via. The rationale of claim 1 applies.
Regarding claim 5, the combination of Chuang and Fan teaches, the semiconductor device of claim 1, further comprising:
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a first source/drain region and a second source/drain region (310/312; drain region / first source region; Chuang Fig. 3; [0011]) over the substrate (202); and
a second frontside contact connecting the second source/drain region to a back end of line (BEOL) through a via, - Chuang teaches contacts (504; contacts; Chuang Fig. 3; [0011]) connecting the drain/source regions (310/312) to the first metal layers, which are redirected through vias to the upper metal layers (508/506; vias / upper metal layers; Chuang Fig. 2; [0012]) of the interconnecting structure, and Fan teaches a frontside interconnect structure with conductive vias over the device (frontside interconnect structure; Fan, [0086]);
wherein: a first frontside contact connects the first source/drain region to a backside of the semiconductor device through a frontside via and the backside via - Fan teaches the source/drain contact (120; source/drain contact; Fan Figs. 1B, 1F; [0018], [0023]) contacting the power via (150; power via; Fan Fig. 1B; [0018]), which contacts the backside conductive feature connected to the power rail directly or by the backside via (240; backside via; Fan Fig. 1F; [0018]). Fan teaches the split frontside/backside source/drain connections; Chuang teaches the device and its BEOL routing.
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Chuang and Fan before him/her, to modify the teachings of a semiconductor device including a backside interconnect as taught by Chuang and to include the teachings of backside interconnect being a backside power delivery structure as taught by Fan, because routing selected source/drain regions to the backside power network while keeping other regions on the frontside BEOL relieves frontside routing congestion and lowers power-rail resistance (Fan [0012] - [0013]). Absent this teaching in Chuang, a person with ordinary skill in the art would be motivated to reach out to Fan while forming the semiconductor feature of Chuang.
Regarding claim 6, the combination of Chuang and Fan teaches, the semiconductor device of claim 1, wherein the high voltage region is a fin field-effect transistor (FET), a planar device, or a nanosheet transistor. Chuang’s NLDMOS has gate structures disposed on the surface of the first N-well and the STI structure, i.e., a planar device (322; gate structures; Chuang Fig. 3; [0011]); Fan further teaches that its backside-powered structures apply to planar FETs, FinFETs and nanosheet FETs (20; nanostructure device; Fan Fig. 1F; [0012], [0025]).
Regarding claim 7, the combination of Chuang and Fan teaches, the semiconductor device of claim 1, wherein the bottom surface of the BDTI and a bottom surface of the backside via are coplanar. As Chuang removes the conductive material outside the trenches, i.e., on the first portion of the dielectric filling layer, the first portion being slightly removed during that removal, so that the backside end of the conductive structure is level with the backside surface of the dielectric filling layer (240/262; conductive structure / first portion of dielectric filling layer; Chuang Fig. 12/13; [0020]).
Regarding claim 8, the combination of Chuang and Fan teaches, the semiconductor device of claim 1, further comprising: a passive device; and an active device connected to the passive device. Chuang teaches active devices on the same substrate (300/600; NLDMOS / logic device; Chuang Fig. 2; [0011], [0014]), and Fan teaches IC cells that include transistors together with integrated capacitors, integrated resistors, integrated inductors and integrated diodes (20; nanostructure devices (transistors); Fan Fig. 1A; [0017]) (100A-100C; IC cells including integrated capacitors/resistors/inductors; Fan Fig. 1A; [0017]). Chuang teaches the active devices; Fan teaches the passive devices integrated with them.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Chuang and Fan before him/her, to modify the teachings of a semiconductor device including a backside interconnect as taught by Chuang and to include the teachings of active device connected to the passive device as taught by Fan, (1) because Fan expressly contemplates integrating capacitors, resistors and inductors with the transistors of the same IC cells ([0017]), avoiding off-chip components; (2) since the modification amounts to combining prior-art elements according to known methods (MPEP 2143(I)(A)); and (3) with a reasonable expectation of success, yielding the predictable result of an active device electrically connected to an on-chip passive device. Absent this teaching in Chuang, a person with ordinary skill in the art would be motivated to reach out to Fan while forming the semiconductor feature of Chuang.
Regarding claim 9, the combination of Chuang and Fan teaches, the semiconductor device of claim 8, wherein an insulating layer (140; fourth isolation layer; Fan Figs. 1B, 11C; [0022], [0077]) isolates a frontside via (150; power via formed in openings 38; Fan Fig. 11F; [0080]-[0081]) from direct contact with gate regions (200; gate structures; Fan Fig. 11B; [0076]) of the active device. Fan forms openings extending through the gate structures and the isolation regions, conformally lines them with the fourth isolation layer, and forms the power via inside that layer.
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Chuang and Fan before him/her, to modify the teachings of a semiconductor device including a backside interconnect as taught by Chuang and to include the teachings of an insulating layer isolating a frontside via from direct contact with gate regions of the active device as taught by Fan, (1) because a dielectric liner between a via and adjacent gate/source-drain features prevents shorting and isolates neighboring devices (Fan [0022], [0078]); (2) since the modification amounts to applying a known via-isolation technique to a similar device (MPEP 2143(I)(D)); and (3) with a reasonable expectation of success, yielding the predictable result of a frontside via electrically isolated from the gate regions. Absent this teaching in Chuang, a person with ordinary skill in the art would be motivated to reach out to Fan while forming the semiconductor feature of Chuang.
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0377945 A1 (Chuang) in view of US 2023/0317566 A1 (Fan).
Regarding claim 19, Chuang teaches, a semiconductor device (800; semiconductor feature; Fig. 12; [0021]), comprising:
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a shallow trench isolation (STI) (206; STI structure; Figs. 3, 13; [0011], [0022]); and
a backside dielectric trench isolation (BDTI) (224; dielectric filling layer, including first portion 262 and second portion 264; Figs. 9, 13; [0017] - [0018], [0022], formed from the backside in a trench disposed beneath the STI structure) below the STI (214; trench “disposed beneath a corresponding one of the STI structures 206”; Fig. 13; [0017]),
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wherein: a top surface (bottom surface in Fig. 7) of the BDTI (224) is connected to the STI (222; bottom wall portion defined by STI 206; Fig. 7; [0017] - [0018]) on a backside of a high voltage region of the semiconductor device (300; NLDMOS / BCD power device; Figs. 2-3; [0011], [0017]),
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a bottom surface of the BDTI (224) is connected to a backside interconnect (252/254/258; connecting feature/connecting pads/metal grid; Fig. 17; [0026]), and
the high voltage region is a fin field-effect transistor (FET), a planar device, or a nanosheet transistor. Chuang’s NLDMOS has gate structures disposed on the surface of the first N-well and the STI structure, i.e., a planar device (322; gate structures; Chuang Fig. 3; [0011]).
But Chuang fails to teach explicitly, the backside interconnect connected to the bottom surface of the BDTI is “a backside power interconnect.”
However, in analogous art, Fan teaches, a backside power delivery structure in which a power rail (250; power rail; Figs. 1F-1G; [0013], [0018]) at the backside of the device is connected, through a backside via (240; backside via; Figs. 1F-1G; [0018]) and a backside conductive feature (180; backside conductive feature; Fig. 1F; [0018], [0085]) formed in backside dielectric layers (160; first backside dielectric layer; Fig. 1F; [0018], [0085]), to a via extending through the STI to a source/drain contact.
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Chuang and Fan before him/her, to modify the teachings of a semiconductor device including a backside interconnect as taught by Chuang and to include the teachings of backside interconnect being a backside power delivery structure as taught by Fan because delivering power from the backside improves frontside signal-routing flexibility and permits wider power rails that reduce resistance and increase power efficiency (Fan, [0012] - [0013]). Absent this teaching in Chuang, a person with ordinary skill in the art would be motivated to reach out to Fan while forming a semiconductor device of Chuang.
Regarding claim 20, the combination of Chuang and Fan teaches, the semiconductor device of claim 19, a backside contact (240; conductive structure; Fig. 13; [0020], [0022]);
the BDTI (264, part of 224; second portion of dielectric filling layer surrounding portion A1; Fig. 13; [0022], [0033]) isolates a backside contact (240) from a substrate (202; semiconductor substrate; Fig. 17; [0010], [0022]).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0377945 A1 (Chuang) in view of US 2023/0317566 A1 (Fan), and further in view of US 2024/0203882 A1 (Lee).
Regarding claim 2, the combination of Chuang and Fan teaches, the semiconductor device of claim 1, further comprising: a carrier wafer bonded to the device, as Chuang bonds a carrier wafer to the top surface of the dielectric structure and the top metal layers (700; carrier wafer; Chuang Figs. 4, 12; [0015], [0021]); and
a bottom interlayer dielectric isolating the substrate from contact with the backside power interconnect. Chuang forms the dielectric blanket layer and the oxide-based (USG) mask layer on the backside of the substrate, beneath the first portion of the dielectric filling layer, the passivation layer and the connecting feature, the composite functioning as the insulator layer of an SOI wafer (210/212; dielectric blanket layer / mask layer; Chuang Figs. 5, 12; [0016], [0027], [0031]).
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But the combination of Chuang and Fan fails to teach explicitly, a bonding oxide bonding the semiconductor device to a carrier wafer.
However, in analogous art, Lee teaches, a backside-power-rail device in which a bonding oxide of silicon oxide is formed on the BEOL layers and a carrier wafer is disposed on the bonding oxide (205; bonding oxide; Lee Fig. 2; [0063]) (215; carrier wafer; Lee Fig. 2; [0064]) (228; backside power rail; Lee Fig. 2; [0065]). Chuang and Fan teach the device of claim 1 and the bottom interlayer dielectric; Lee teaches the bonding oxide.
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Chuang, Fan and Lee before him/her, to modify the teachings of a semiconductor device including a carrier wafer as taught by Chuang and to include the teachings of a bonding oxide bonding the semiconductor device to a carrier wafer as taught by Fan because Chuang requires a carrier wafer bonded to the frontside dielectric to support the structure during substrate thinning ([0015]) and Lee identifies a silicon-oxide bonding layer as the interface for such carrier bonding in a backside-power device ([0063] - [0064]). Absent this teaching in Chuang and Fan, a person with ordinary skill in the art would be motivated to reach out to Lee while forming the semiconductor feature of Chuang.
Allowable Subject Matter
Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if rewritten to overcome the rejections under 35 U.S.C. 112(b) set forth in this Office action.
Regarding claim 4, the closest prior art of record, US 2023/0377945 A1 (Chuang), in conjunction with US 2023/0317566 A1 (Fan), and in combination with the other claimed features, fails to disclose, “an oxide layer over lower portions of sidewalls of the STI and over the BDTI; and an insulating layer over sidewalls of a frontside via, wherein: the insulating layer isolates the frontside via from direct contact with the STI,” in combination with the additionally claimed features, as are claimed by the Applicant. Chuang’s trench 214 terminates at the STI structure 206, so that the dielectric filling layer 224 lines only the substrate side wall portion 220 and the bottom wall portion 222 defined by the STI ([0017]-[0018]); no oxide layer is disposed over lower portions of the STI sidewalls. Fan’s first backside dielectric layer 160 is formed on the bottom surfaces of the isolation regions 36 ([0085]), not over their sidewalls, and although Fan’s fourth isolation layer 140 lines the power via 150 ([0022], [0077]), no reference of record teaches or renders obvious the recited oxide layer over the lower STI sidewalls and the BDTI together with the insulating layer on the frontside via.
Specifically, the aforementioned ‘an oxide layer over lower portions of sidewalls of the STI and over the BDTI,’ together with the insulating layer isolating the frontside via from the STI, is material to the inventive concept of the application at hand to maintain continuous electrical isolation between the backside contact, the STI and the substrate throughout the device ([0075], [0078]).
Examiner’s Note (Additional Prior Arts)
The examiner included a few prior arts which were not used in the rejection but are relevant to the disclosure.
1. US 2021/0202385 A1 (Huang) - A transistor structure having STI-defined active regions, a backside power rail on the back side of the substrate, and a backside contact feature interposed between the backside power rail and a source/drain feature.
2. US 2023/0377949 A1 (Syue) - Conductive connectors disposed within deep trench isolation structures extending through device substrates to interconnect vertically stacked high-voltage devices.
3. US 2024/0113193 A1 (Li) - Backside contacts formed from shallow placeholders after carrier-wafer bonding and substrate removal stopping on the STI, connected to a backside power distribution network.
4. US 2023/0093101 A1 (Xie) - Backside electrical contacts to buried power rails formed after carrier-wafer bonding and substrate thinning, with a backside ILD and backside power distribution network.
5. US 2010/0244179 A1 (Voldman) - A through-wafer via structure bounding a latch-up-sensitive structure to block parasitic carrier injection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to S M SOHEL IMTIAZ whose telephone number is (408) 918-7566. The examiner can normally be reached on 8AM-5PM, M-F, PST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S M SOHEL IMTIAZ/Primary Patent Examiner
Art Unit 2812
09/23/2026
