Prosecution Insights
Last updated: October 01, 2026
Application No. 18/773,592

MANUFACTURING METHOD OF PACKAGE STRUCTURE

Non-Final OA §102§103§112
Filed
Jul 16, 2024
Priority
May 28, 2020 — continuation of 11/233,035 +1 more
Examiner
LE, THAO P
Art Unit
Tech Center
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
93%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 93% — above average
93%
Career Allowance Rate
754 granted / 814 resolved
+32.6% vs TC avg
Minimal -1% lift
Without
With
+-0.8%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 10m
Avg Prosecution
24 currently pending
Career history
826
Total Applications
across all art units

Statute-Specific Performance

§101
1.2%
-38.8% vs TC avg
§103
43.2%
+3.2% vs TC avg
§102
42.0%
+2.0% vs TC avg
§112
3.2%
-36.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 814 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-3, 5, 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al., U.S. Pub. No. 2019/0326259. Regarding claim 1, Yu discloses: a manufacturing method for a package structure, comprising (Yu describes manufacturing multi-level packages, abstract, Figs. 8-9): providing a die 26, forming and bonding a die stack structure to the die (die 26 is a memory die stack [0039], or levels of device dies including dies 26, 42, and 56), fusion bonding a support structure onto the die stack structure ([0039]-[0040]: dummy wafer 24 provides the support structure and die 26 is directly fusion bonding to dielectric layer 23 on dummy wafer 24), wherein a width of the support structure is larger than a width of the die stack structure (the dummy support 24 extends laterally beyond the device dies/memory die stack 26, Fig. 8) and sidewalls of the support structure and the die stack structure are laterally shifted (where the dummy support 24 extends beyond the edge of the memory die stack 26, its sidewall is laterally displaced from the corresponding die-stack sidewall, Fig. 8), and forming an insulation structure on the die, laterally wrapping around the die stack structure (the encapsulating materials 59 is formed on device die 56, encapsulating material 50 is formed around second level dies 42, and encapsulating 33 is formed around first level dies 26, Fig. 9) and the support structure (Fig. 18: encapsulating material 33 encircled dummy support 24’). Regarding claim 2, Yu discloses wherein the insulation structure is formed after fusion bonding the support structure onto the die stack structure ([0039]-[0040], Figs. 11-12: wherein device dies 26 are fusion bonded to layer 23 of dummy wafer 24, and subsequent process steps include forming the encapsulating materials as described with respect to Figs. 4-9). Regarding claim 3, Yu discloses forming the insulation structure comprises forming an insulation material layer to cover the die stack structure and the support structure and performing a planarization process to partially remove the insulation material layer ([0023], [0029], [0032]). Regarding claim 5, Yu discloses wherein the insulation structure comprises an encapsulant formed after fusion bonding the support structure onto the die stack structure, and the encapsulant at least wraps around the sidewall of the support structure (Fig. 9: the encapsulating materials 59 is formed on device die 56, encapsulating material 50 is formed around second level dies 42, and encapsulating 33 is formed around first level dies 26; Fig. 18: encapsulating material 33 encircled dummy support 24’). Regarding claim 9, Yu discloses wherein the die stack structure is formed with a plurality of semiconductor dies electrically connected with one another by through semiconductor vias (Fig. 8-9: multi-level stacking dies and through vias). Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(d): (d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers. The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph: Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers. Claim 8 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Applicants may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements. Claim 1 requires the width of the support structure to be larger than the width of the die structure, whereas claim 8 requires the width of the support structure to be smaller than the width of the die structure. The limitation of claim 8 is inconsistent with the limitation of claim 1 from which claim 8 depends. Claim 8 recites a width relationship contrary to the width relationship required by claim 1. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 10-12, 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Uzoh et al., U.S. Pub. No. 2020/0411483, in view of Yu, U.S. Pub. No. 2019/0326259. Regarding claim 10, Uzoh discloses a manufacturing method for a package structure, comprising (Fig. 15): providing a die 102, forming and bonding a die stack structure (upper dies 102’, 102’’, 102’’’) to the die 102, bonding a support structure (dummy die 1504) onto the die stack structure, forming an insulation structure 1502/1506 covering the die and laterally wrapping around the die stack structure and the support structure. Uzoh fails to disclose wherein sidewalls of the die, the support structure, and the die stack structure are laterally offset. Yu discloses the package structure (Fig. 18) wherein sidewalls of the die, the support structure, and the die stack structure are laterally offset (dies 26, 42, and 56 and support structure 24/24’). It would have been obvious to one having ordinary skill in the art at the time the invention was made to modify Uzoh in view of Yu to reduce package warpage stress, increase mechanical support, and improve reliability. Regarding claim 11, Uzoh discloses forming lower dielectric layers 1502 wrapping around the die stack structure before bonding the support structure 1504 (Fig. 15). Regarding claim 12, Yu discloses wherein forming the die stack structure comprises (Figs. 1-18): bonding a lower die 26 to the die (Yu discloses that die 26 may itself be a single memory die or memory-die stack), forming a first lower dielectric layer 33 on and laterally aside the lower die, bonding a middle die 42 to the lower die 26, forming a second lower dielectric layer 50/52 on the first lower dielectric layer and laterally aside the middle die, bonding an upper die 56 to the middle die, and forming a third lower dielectric layer 59/64 on the second lower dielectric layer and laterally aside the upper die. Regarding claim 14, Yu discloses forming a first isolation layer 30 on the die before bonding the die stack structure to the die (Fig. 9). Regarding claim 15, Yu discloses bonding a lower die to the die after forming the first isolation layer, forming a second isolation layer on the lower die after bonding the lower die to the die, bonding a middle die to the lower die, forming a third isolation layer on the middle die after bonding the middle die to the lower die, and bonding an upper die to the middle die (Figs. 1-18). Regarding claim 16, Yu discloses wherein the insulation structure is formed after fusion bonding the support structure 24 onto the die stack structure (Figs 1-9, [0039]). Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Uzoh et al., U.S. Pub. No. 2020/0411483, in view of Modi, U.S Pub. No. 2022/0102242. Regarding claim 10, Uzoh discloses a manufacturing method for a package structure, comprising (Fig. 15): providing a die 102, forming and bonding a die stack structure (upper dies 102’, 102’’, 102’’’) to the die 102 including dies with a substrate, providing a support structure (dummy die 1504) with a dielectric bonding film, forming an insulation structure 1502/1506 covering the die and laterally wrapping around the die stack structure and the support structure. Uzoh fails to disclose wherein the support structure has a thermal conductivity larger than that of the die stack structure. Modi discloses the support structure (dummy die 340) has a thermal conductivity larger than that of the die stack structure ([0066]-[0067]). It would have been obvious to one having ordinary skill in the art at the time the invention was made to modify Uzoh in view of Modi to have the support structure with a higher thermal conductivity than the die in order to improve thermal characteristics and heat conduction of the packaged device. Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Uzoh et al., U.S. Pub. No. 2020/0411483, in view of Modi, U.S Pub. No. 2022/0102242, further in view of Yu, U.S. Pub. No. 2019/0326259. Regarding claim 18, Uzoh and Modi fail to disclose wherein bonding the support structure with the die stack structure includes performing a fusion bonding process to bond the dielectric with the substrate. Yu discloses wherein bonding the support structure with the die including fusion bonding process. It would have been obvious to one having ordinary skill in the art at the time the invention was made to use fusion bonding process as disclosed in Yu in the method of Uzoh and Modi in order to provide high bond strength, reliable bonding between the structures without requiring an intervening adhesive layer. Allowable Subject Matter Claims 4, 6-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior made of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed limitations having the limitations of claims 1 and 2, further comprising performing a dicing process cutting through the insulation structure, and a sidewall of the die is aligned with a sidewall of the insulation structure (claim 4), the limitations of claims 1 and 5, wherein the insulation structure comprises a dielectric structure formed before fusion bonding the support structure onto the die stack structure, and the dielectric structure disposed between the encapsulant and the die covers the sidewall of the die stack structure (claim 6). Claims 14, 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior made of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed limitations having the limitations of claim 10 or claim 17, further comprising performing a dicing process cutting through the insulation structure, and a sidewall of the die is aligned with a sidewall of the insulation structure. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to THAO P LE whose telephone number is (571)272-1785. The examiner can normally be reached on Monday-Friday 9AM-6PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). /THAO P LE/Primary Examiner, Art Unit 2818
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Prosecution Timeline

Jul 16, 2024
Application Filed
Sep 04, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
93%
Grant Probability
92%
With Interview (-0.8%)
1y 10m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 814 resolved cases by this examiner. Grant probability derived from career allowance rate.

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