DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDSs) submitted on 7/16/2024 and 7/29/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Double Patenting (Statutory)
A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101.
Claim 6 is rejected under 35 U.S.C. 101 as claiming the same invention as that of claim 2 of prior U.S. Patent No. US 12,074,070 B2 (will be referred as Hsu-070). This is a statutory double patenting rejection.
Instant Application- 18/773,598
US 12,074,070 B2 (Hsu-070).
Claim 1:
A semiconductor device, comprising:
a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion;
a first isolation structure on the SDB structure,
wherein the first isolation structure comprises:
a cap layer on the SDB structure; and
a dielectric layer on the cap layer;
a shallow trench isolation (STI) adjacent to the SDB structure; and
a second isolation structure on the STI.
Claim 6:
The semiconductor device of claim 1, wherein
top surfaces of the SDB structure and the STI are coplanar.
Claim 1:
A semiconductor device, comprising:
a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion;
a first isolation structure on the SDB structure;
a shallow trench isolation (STI) adjacent to the SDB structure,
wherein top surfaces of the STI and the SDB structure are coplanar; and
a second isolation structure on the STI.
Claim 2:
The semiconductor device of claim 1,
wherein the first isolation structure comprises:
a cap layer on the SDB structure; and
a dielectric layer on the cap layer.
Double Patenting (Non-Statutory)
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 2 of U.S. Patent No. US 12,074,070 B2 (will be referred as Hsu-070).
Instant Application- 18/773,598
US 12,074,070 B2 (Hsu-070).
Claim 1:
A semiconductor device, comprising:
a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion;
a first isolation structure on the SDB structure,
wherein the first isolation structure comprises:
a cap layer on the SDB structure; and
a dielectric layer on the cap layer;
a shallow trench isolation (STI) adjacent to the SDB structure; and
a second isolation structure on the STI.
Claim 1:
A semiconductor device, comprising:
a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion;
a first isolation structure on the SDB structure;
a shallow trench isolation (STI) adjacent to the SDB structure,
wherein top surfaces of the STI and the SDB structure are coplanar; and
a second isolation structure on the STI.
Claim 2:
The semiconductor device of claim 1,
wherein the first isolation structure comprises:
a cap layer on the SDB structure; and
a dielectric layer on the cap layer.
Regarding claim 1, Hsu-070 claim 2 teaches all the limitations of claim 1 as shown in the table above. The extra limitation of Hsu-070’s claim 1, reciting “wherein top surfaces of the STI and the SDB structure are coplanar”, is within the scope of claim 1.
Claims 2-5 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 3-6 of U.S. Patent No. US 12,074,070 B2 (Hsu-070), respectively.
Instant Application- 18/773,598
US 12,074,070 B2 (Hsu-070).
Claim 2:
The semiconductor device of claim 1, wherein
the dielectric layer comprises a T-shape.
Claim 3:
The semiconductor device of claim 1, wherein
the cap layer and the dielectric layer comprise a T-shape altogether.
Claim 4:
The semiconductor device of claim 1, wherein the cap layer comprises a U-shape.
Claim 5:
The semiconductor device of claim 1, wherein
the cap layer and the dielectric layer comprise different materials.
Claim 7:
The semiconductor device of claim 1, wherein
bottom surfaces of the first isolation structure and the second isolation structure are coplanar.
Claim 3:
The semiconductor device of claim 2, wherein
the dielectric layer comprises a T-shape.
Claim 4:
The semiconductor device of claim 2, wherein
the cap layer and the dielectric layer comprise a T-shape altogether.
Claim 5:
The semiconductor device of claim 2, wherein
the cap layer comprises a U-shape.
Claim 6:
The semiconductor device of claim 2, wherein
the cap layer and the dielectric layer comprise different materials.
Claim 8:
The semiconductor device of claim 1, wherein bottom surfaces of the first isolation structure and the second isolation structure are coplanar.
Regarding claim 2, Hsu-070’s claim 2 teaches all the limitations of claim 1, and Hsu-070’s claim 3 recites all the limitations of claim 2.
Regarding claim 3, Hsu-070’s claim 2 teaches all the limitations of claim 1, and Hsu-070’s claim 4 recites all the limitations of claim 3.
Regarding claim 4, Hsu-070’s claim 2 teaches all the limitations of claim 1, and Hsu-070’s claim 5 recites all the limitations of claim 4.
Regarding claim 5, Hsu-070’s claim 2 teaches all the limitations of claim 1, and Hsu-070’s claim 6 recites all the limitations of claim 5.
Claim 7 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 7 of U.S. Patent No. US 12,074,070 B2 (Hsu-070), and further in view of Tseng (US 2016/0276429 A1)
Instant Application- 18/773,598
US 12,074,070 B2 (Hsu-070).
Claim 1:
A semiconductor device, comprising:
a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion;
a first isolation structure on the SDB structure,
wherein the first isolation structure comprises:
a cap layer on the SDB structure; and
a dielectric layer on the cap layer;
a shallow trench isolation (STI) adjacent to the SDB structure; and
a second isolation structure on the STI.
Claim 7:
The semiconductor device of claim 1, wherein
bottom surfaces of the first isolation structure and the second isolation structure are coplanar.
Claim 1:
A semiconductor device, comprising:
a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion;
a first isolation structure on the SDB structure;
a shallow trench isolation (STI) adjacent to the SDB structure,
wherein top surfaces of the STI and the SDB structure are coplanar; and
a second isolation structure on the STI.
Claim 7:
The semiconductor device of claim 1, wherein
bottom surfaces of the first isolation structure and the second isolation structure are coplanar.
Regarding claim 7, Hsu-070’s claim 8 teaches all the limitations of claim 7, except that
the first isolation structure comprises:
a cap layer on the SDB structure; and
a dielectric layer on the cap layer.
Tseng, on the other hand, teaches an isolation structure (comprising gate dielectric
layers 311 and spacer layers 321, Fig. 6, [0025]-[0026]) on a single diffusion barrier structure (insulating layer 104, Fig. 6, [0025]), wherein the isolation structure (comprising gate dielectric
layers 311 and spacer layers 321, Fig. 6) comprises
a cap layer (gate dielectric layer 311, Fig. 6) on the SDB structure (insulating layer 104, Fig. 6); and
a dielectric layer (spacer layers 321, Fig. 6) on the cap layer (gate dielectric layers 311, Fig. 6).
Tseng further discloses that including the spacer layer prevents the trenches between the fins becaming larger during processing of the dummy gate structure, which includes the gate dielectric layer. Furthermore, forming dummy gate structures on the single diffusion barriers as part of an isolation structure is common in finFET devices, as also evidenced by Jha (see dummy gate 120A in Fig. 7, US 2019/0035633 A1). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention who is motivated to obtain a finFET device with dummy gates would be motivated to have the isolation structure in the semiconductor device of Hsu-070 to include a cap layer on the SDB structure and a dielectric layer on the cap layer, as taught by Tseng, to be able to manufacture the device with minimal degradation of the distance between the fins.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 4-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tseng (US 2016/0276429 A1).
Regarding claim 1, Tseng teaches a semiconductor device (semiconductor device, Figs. 6, [0025]), comprising:
a single diffusion break (SDB) structure (insulating layer 104 in the middle, Fig. 6, [0018]) dividing a fin-shaped structure (fin shaped structure 101, Fig. 6, [0025]) into a first portion (the portion on the left side of middle insulating layer 104, Fig. 6) and a second portion (the portion on the right side of middle insulating layer 104, Fig. 6);
a first isolation structure (comprising gate dielectric layer 311 and spacer layer 321, Fig. 6, [0025]) on the SDB structure (insulating layer 104 in the middle, Fig. 6), wherein the first isolation structure (comprising gate dielectric layer 311 and spacer layer 321, Fig. 6) comprises:
a cap layer (gate dielectric layer 311, Fig. 6, [0025]) on the SDB structure (insulating layer 104 in the middle, Fig. 6); and
a dielectric layer (spacer layer 321, Fig. 6, [0026]) on the cap layer (gate dielectric layers 311, Fig. 6);
a shallow trench isolation (STI) (insulating layer 104 on the left, Fig. 6, [0018]: “the insulating layer 104 formed in the shallow trench 102 may be function as a shallow trench isolation (STI).” (see Fig. 2 for trench 102) adjacent to the SDB structure (insulating layer 104 in the middle, Fig. 6); and
a second isolation structure (comprising gate dielectric layer 313 and spacer layer 322, Fig. 6, [0025]) on the STI (insulating layer 104 on the left, Fig. 6).
Regarding claim 4, Tseng teaches the semiconductor device of claim 1, wherein the cap layer (gate dielectric layers 311, Fig. 6) comprises a U-shape (see Fig. 6).
Regarding claim 5, Tseng teaches the semiconductor device of claim 1, wherein the cap layer (gate dielectric layers 311, Fig. 6, [0018]: “silicon oxide”) and the dielectric layer (spacer layer 321, Fig. 6, [0024]-[0025]: the spacer layer 321 is formed by etching the material layer 320 which can be silicon nitride) comprise different materials (silicon oxide vs silicon nitride).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Tseng (US 2016/0276429 A1) as applied to claims 1 and 4-5 above, and further in view of Jha (US 2019/0035633 A1).
Regarding claim 2, while Tseng teaches the semiconductor device of claim 1,
Tseng does not teach that the dielectric layer comprises a T-shape.
Jha, on the other hand, teaches a semiconductor device (Fig. 7, [0040]) comprising a single diffusion break (SDB) structure (STI oxide structure 260, Fig. 7, [0039]) and an isolation structure (comprising nitride layer 270 (corresponds to the cap layer) and insulating material 280 (corresponds to the dielectric layer), Fig. 7, [0024]) wherein
the dielectric layer (insulating material 280, Fig. 7) comprises a T-shape (see Fig. 7).
Jha further discloses that the dielectric layer (insulating material 280, Fig. 7) and the cap layer (nitride layer 270, Fig, 7) as disclosed by Jha prevents degradation of the aspect ratio of the isolation structure and reduces source/drain facet degradation during manufacturing the device. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to replace the isolation structure in the semiconductor device of Tseng with the isolation structure taught by Jha to obtain the benefits of reducing the degradation of both the aspect ratio of the isolation structure and the source/drain facet. Thus, the combination of Tseng and Jha meets the limitation that the dielectric layer comprises a T-shape.
Regarding claim 3, while Tseng teaches the semiconductor device of claim 1,
Tseng does not teach that the cap layer and the dielectric layer comprise a T-shape altogether.
Jha, on the other hand, teaches a semiconductor device (Fig. 7, [0040]) comprising a single diffusion break (SDB) structure (STI oxide structure 260, Fig. 7, [0039]) and an isolation structure (comprising nitride layer 270 (corresponds to the cap layer) and insulating material 280 (corresponds to the dielectric layer), Fig. 7, [0024]) wherein
the cap layer (nitride layer 270) and dielectric layer (insulating material 280, Fig. 7) comprise a T-shape altogether (see Fig. 7).
Jha further discloses that the dielectric layer (insulating material 280, Fig. 7) and the cap layer (nitride layer 270, Fig, 7) as disclosed by Jha prevents degradation of the aspect ratio of the isolation structure and reduces source/drain facet degradation during manufacturing the device. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to replace the isolation structure in the semiconductor device of Tseng with the isolation structure taught by Jha to obtain the benefits of reducing the degradation of both the aspect ratio of the isolation structure and the source/drain facet. Thus, the combination of Tseng and Jha meets the limitation that the cap layer and the dielectric layer comprise a T-shape altogether.
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Tseng (US 2016/0276429 A1) as applied to claims 1 and 4-5 above.
Regarding claim 6, while Tseng teaches the semiconductor device of claim 1,
Tseng does not explicitly teach that top surfaces of the SDB structure (insulating layer 104 in the middle, Fig. 6) and the STI (insulating layer 104 on the left, Fig. 6) are coplanar.
Tseng, however, teaches that the insulating layers 104 are formed through a flowable chemical vapor deposition (FCVD) process, and a chemical mechanical polishing (CMP) process and an etching back process ([0018]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would understand that the top surfaces of insulating layers will coplanar after the processes above.
Regarding claim 7, while Tseng teaches the semiconductor device of claim 1,
Tseng does not explicitly teach that bottom surfaces of the first isolation structure and the second isolation structure are coplanar.
Tseng, however, teaches that the insulating layers 104 are formed through a flowable chemical vapor deposition (FCVD) process, and a chemical mechanical polishing (CMP) process and an etching back process ([0018]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would understand that the top surfaces of insulating layers will coplanar after the processes above. Because the isolation structures are directly formed in the top surfaces of insulating layers 104, bottom surfaces of the first isolation structure and the second isolation structure are coplanar.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Park (US 2015/0325575 A1) teaches a semiconductor device with dummy gates, which is relevant to all claims.
Yu (US 9368496 B1) teaches a semiconductor device with single diffusion break structures, which is relevant to all claims.
Wang (US 2018/0068998 A1) teaches a semiconductor device with single diffusion break structures, which is relevant to all claims.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ILKER OZDEN whose telephone number is (703)756-5775. The examiner can normally be reached Monday - Friday 8:30am-5:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ILKER NMN OZDEN/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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