DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102/103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 17, 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 9627312 B2 Childs et al hereafter “Childs”.
Claim 17 Childs teaches a method of forming a semiconductor structure, comprising:
forming a capacitor (comprising at least 234, 226, 226, 227, 232, 228 fig. 2);
forming a first conductor (238 fig. 2 and connected vias in 217 illustrated fig. 2) and a second conductor (240 fig. 2 and connected vias in 217 fig. 2) at least partially surrounded by the capacitor [sufficiently illustrated fig. 2]; and
forming a first bump (290 292 electrically connected to 238 fig. 2) over the first conductor and a second bump (290 and 292 electrically connected 240 fig. 2) over the second conductor [sufficiently illustrated fig. 2].
Claim 19 Childs teaches as shown above the method of Claim 17, wherein the first conductor and the second conductor are at least partially exposed prior to the formation of the first bump and the second bump [sufficiently illustrated fig. 2 the first and the second conductors are electrically exposed to the formation and/or structure comprising the first and the second bumps].
Claim 20 Childs teaches as shown above the method of Claim 17, wherein the first bump and the second bump are electrically connected to the capacitor via the first conductor and the second conductor respectively [sufficiently illustrated fig. 2].
Claim(s) 1-2, 4-5, 7, 11-13, 16, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Childs as shown above and in further view of US 20140183693 A1 Tsai et al hereafter “Tsai” and NPL "Capacitance Measurements of Two-Dimensional and Three-Dimensional IC Interconnect Structures by Quasi-Static C-V Technique," Stucchi et al hereafter “Stucchi”.
Claim 1 Childs teaches a method of detecting a semiconductor structure, comprising:
providing a capacitor (comprising 234, 235, 230, 227 and 226 fig. 2), a first dielectric (comprising 236, 232, 228, and 224 fig. 2) surrounding the capacitor (comprising 236, 232, 228, and 224 fig. 2), and first and second conductors (240 and 238 and the via/interconnect structures of 217 sufficiently illustrated fig. 2) at least partially surrounded by the capacitor and the first dielectric [sufficiently illustrated fig. 2, the part of the first and second conductors within 220]; and
Childs does not teach determining an electrical property of the capacitor through the first conductor and the second conductor.
Tsai teaches determining an electrical property of a capacitor throughout a manufacturing process [sufficiently disclosed “by probing the capacitance values of these capacitors 46, the manufacturing process may be monitored”]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Childs in view of Tsai such that “determining an electrical property of the capacitor” Occurs.
A person of ordinary skill in the art would have been motivated to make this modification to enable monitoring of the manufacturing process and uniformity of the passivation [Paragraph 0026 Tsai]
Stucchi teaches determining an electrical property (“capacitance” Fig. 11) of a capacitor (Cx Fig. 11) through a first conductor (PAD Wire A fig. 11) and a second conductor (PAD Wire B fig. 11)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Childs in view of Tsai in further view of Stucchi such that “determining an electrical property of the capacitor through the first conductor and the second conductor”.
A person of ordinary skill in the art would have been motivated to make this modification to determine the capacitance of the capacitor accurately and noise-free [page 1986 Column 1 paragraph 2 Stucchi “The measurement settings for obtaining noise-free and accurate QSCV measurements” and “(15) yields more accurate results”].
Combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. In this case it is methods to determine the capacitance of a capacitor.
Claim 2 Childs in view of Tsai and Stucchi teach the method of Claim 1, wherein the determination of the electrical property of the capacitor includes obtaining a capacitance of the capacitor [met in view of Tsai and Stucchi as shown above in claim 1].
Claim 4 Childs in view of Tsai and Stucchi teach the method of Claim 1, wherein the first conductor and the second conductor are at least partially exposed during the determination of the electrical property of the capacitor [met in view of Stucchi fig. 11 illustrates the first and second conductor must be exposed to the probes of the capacitance meter to make the measurement].
Claim 5 Childs in view of Tsai and Stucchi teach the method of Claim 1, further comprising disposing a second dielectric (223 fig. 2) over the first dielectric and surrounding the first conductor and the second conductor [sufficiently illustrated fig. 2], wherein the first conductor and the second conductor are at least partially exposed through the second dielectric [met under broadest reasonable interpretation the first conductor and the second conductor are electrically exposed to the capacitor and electrically exposed to electrical bumps 292, it is electrically exposed to the gnd and electrically exposed to the +V and physically exposed to the insulating layer of 217, illustrated fig. 2].
Claim 7 Childs in view of Tsai, and Stucchi as shown above the method of Claim 5, wherein the determination of the electrical property of the capacitor is performed after the disposing the second dielectric [this limitation is met in view of Tsai as shown above one would want to monitor the capacitor throughout the process including after disposing the second dielectric to reduce process costs and/or to verify no defects have been introduced after the process step].
Claim 11 Childs in view Tsai and Strucchi teaches as shown above the method of Claim 1, wherein the first conductor is electrically connected to the second conductor via the capacitor [sufficiently illustrated fig. 2 Childs].
Claim 12 Childs teaches a method of inspecting a semiconductor structure, comprising:
providing a capacitor (comprising at least 226, 227, 230, 234, 235, 228, 232 fig. 2), a first dielectric (comprising at least 236 and 224 fig. 2) surrounding the capacitor, and first and second conductors (comprising at least 240, 238 and the vias 217 of fig. 2) at least partially surrounded by the capacitor and the first dielectric, wherein the capacitor includes:
a first electrode (226 fig. 2);
a first dielectric layer (228 and/or 232 fig. 2) over the first electrode; and
a second electrode (234 fig. 2) over the first dielectric layer,
Childs does not teach obtaining a capacitance of the capacitor through the first conductor and the second conductor.
Tsai teaches obtaining an electrical property of a capacitor throughout a manufacturing process [sufficiently disclosed “by probing the capacitance values of these capacitors 46, the manufacturing process may be monitored”]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Childs in view of Tsai such that “obtaining an electrical property of the capacitor” Occurs.
A person of ordinary skill in the art would have been motivated to make this modification to enable monitoring of the manufacturing process and uniformity of the passivation [Paragraph 0026 Tsai]
Stucchi teaches obtaining an electrical property (“capacitance” Fig. 11) of a capacitor (Cx Fig. 11) through a first conductor (PAD Wire A fig. 11) and a second conductor (PAD Wire B fig. 11)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Childs in view of Tsai in further view of Stucchi such that “obtaining an electrical property of the capacitor through the first conductor and the second conductor”.
A person of ordinary skill in the art would have been motivated to make this modification to obtain the capacitance of the capacitor accurately and noise-free [page 1986 Column 1 paragraph 2 Stucchi “The measurement settings for obtaining noise-free and accurate QSCV measurements” and “(15) yields more accurate results”].
Combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. In this case it is combining known methods for the purpose of determining the capacitance of a capacitor.
Claim 13 Childs in view of Tsai and Stucchi teach as shown above the method of Claim 12, wherein the first conductor is electrically connected to the first electrode, and the second conductor is electrically connected to the second electrode [sufficiently illustrated fig. 2].
Claim 16 Childs in view of Tsai and Stucchi teaches as shown above the method of Claim 12, wherein the first electrode is isolated from the second conductor, and the second electrode is isolated from the first conductor [sufficiently illustrated fig. 2].
Claim 18 Childs teaches the method of Claim 17.
Childs does not teach performing an electrical measurement of the capacitor through the first conductor and the second conductor, wherein the electrical measurement of the capacitor is performed prior to the formation of the first bump and the second bump.
Tsai teaches performing an electrical measurement of a capacitor throughout a manufacturing process [sufficiently disclosed “by probing the capacitance values of these capacitors 46, the manufacturing process may be monitored”]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Childs in view of Tsai such that “performing an electrical measurement” Occurs.
A person of ordinary skill in the art would have been motivated to make this modification to enable monitoring of the manufacturing process and uniformity of the passivation [Paragraph 0026 Tsai]
Stucchi teaches performing an electrical measurement (“capacitance” Fig. 11) of a capacitor (Cx Fig. 11) through a first conductor (PAD Wire A fig. 11) and a second conductor (PAD Wire B fig. 11)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Childs in view of Tsai in further view of Stucchi such that “performing an electrical measurement of the capacitor through the first conductor and the second conductor”.
A person of ordinary skill in the art would have been motivated to make this modification to performing an electrical measurement of the capacitor accurately and noise-free [page 1986 Column 1 paragraph 2 Stucchi “The measurement settings for obtaining noise-free and accurate QSCV measurements” and “(15) yields more accurate results”].
Combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. In this case it is methods to determine the capacitance of a capacitor.
Claim(s) 6, and 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Childs in view of Tsai and Stucchi as shown above and in further view of US 20060137905 A1 Kariya et al hereafter “Kariya”.
Claim 6 Childs in view of Tsai and Stucchi teaches as shown above the method of Claim 5.
Childs does not teach wherein the first conductor and the second conductor are at least partially exposed through the second dielectric by removing a portion of the second dielectric on the first conductor and the second conductor.
Kariya teaches providing a capacitor (620 fig. 16), a first dielectric (comprising but not limited to 610 and 628 fig. 16) surrounding the capacitor, and first and second conductors (comprising 266, 261, 262, 267, 247, 262 fig. 16) at least partially surrounded by the capacitor and the first dielectric [sufficiently illustrated fig. 16], disposing a second dielectric (670 fig. 16) over the first dielectric and surrounding the first conductor and the second conductor [sufficiently illustrated fig. 16];
wherein the first conductor and the second conductor are at least partially exposed through the second dielectric by removing a portion of the second dielectric on the first conductor and the second conductor [sufficiently illustrated fig. 17].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the processes of Childs in view of Tsai and Stucchi in further view of Kariya such that “the first conductor and the second conductor are at least partially exposed through the second dielectric by removing a portion of the second dielectric on the first conductor and the second conductor.”
A person of ordinary skill in the art would have been motivated to make this modification to reduce the degradation of the decoupling effect of the chip capacitor and reduce power loss from the chip capacitor [Paragraph 0018 Kariya].
In addition, combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. In this case it is equivalent processes for the purpose of forming a chip capacitor.
Claim 8 Childs in view of Tsai, and Stucchi teaches as shown above the method of Claim 1, wherein after the determination of the electrical property of the capacitor [this limitation is met in view of Tsai as shown above one would want to monitor the capacitor throughout the process including after disposing the second dielectric to reduce process costs and/or to verify no defects have been introduced after the process step], further comprising:
disposing a third dielectric layer [not labeled but sufficiently illustrated fig. 2, the dielectric layer of 217] to partially cover the first conductor and the second conductor [illustrated fig. 2];
forming a UBM layer [290 fig. 2] over the first conductor and the second conductor.
Childs does not teach a third dielectric layer being a polymer layer; nor the UBM surrounded by the polymer layer.
Kariya teaches a third dielectric layer (470 fig. 7 and/or the equivalent structure 670 fig. 16-17) is a polymer [disclosed with sufficient specificity “polyimide” paragraph 0053].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Childs in view of Tsai and Stucchi in further view of Kariya such that ‘the third dielectric layer is a polymer layer’.
A person of ordinary skill in the art would have been motivated to make this modification to adequately relax the stress that occurs due to thermal expansion between the elements of the device and the substrate [Paragraph 0053 Kariya].
Tsai teaches a UBM (50 fig. 7) surrounded by a dielectric layer (48 fig. 48).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Childs in view of Tsai, Stucchi, and Kariya such that ‘the UBM is surrounded by the polymer layer’.
A person of ordinary skill in the art would have been motivated to make this modification to improve the isolation surrounding the polymer layer.
Substituting equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. In this case it is substituting one known UBM structure for another known UBM structure for the purpose of interconnecting a solder ball to a chip capacitor [sufficiently illustrated fig. 7 Tsai and fig. 2 Childs].
Claim 9 Childs in view of Tsai, Stucchi, and Kariya teach as shown above the method of Claim 8, wherein the first conductor and the second conductor are entirely covered by the polymer layer and the UBM layer [sufficiently illustrated fig. 2 of Childs in view of the modification of Tsai and Kariya].
Claim 10 Childs in view Tsai, Stucchi, and Kariya teach as shown above the method of Claim 8, further comprising placing a solder ball (sufficiently illustrated by element 292 fig. 2) on the UBM layer, wherein the determination of the electrical property of the capacitor is performed prior to the placement of the solder ball [this limitation is met in view of Tsai as shown above one would want to monitor the capacitor throughout the process including after disposing the second dielectric to reduce process costs and/or to verify no defects have been introduced by manufacturing steps].
Claims 3, 14, and 15 is rejected under 35 U.S.C. 103 as being unpatentable over Childs in view of Tsai and Stucchi as shown above and in further view of US 20170367187 A1 Chae et al hereafter “Chae”.
Claim 3 Childs in view of Tsai and Stucchi teaches as shown above the method of Claim 2.
Childs does not explicitly teach the capacitance of the capacitor determines a defect of the capacitor.
Chae teaches when measuring capacitance of a capacitor if the measured value is lower than a predetermined threshold a capacitance defect is determined sufficiently disclosed Paragraph 130 “here the value of (B+C)/A exceeds 1.761, had measured capacitance values lower than target capacitance values, and were thus designated as having a capacitance defect”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Childs in view of such that “the capacitance of the capacitor determines a defect of the capacitor”.
Substituting and/or combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. In this case it is known means/processes for determining a defect by measuring capacitance.
Claim 14 Childs in view of Tsai and Stucchi teach as shown above the method of Claim 12,
Childs does not explicitly teach the capacitor with a defect is identified by the obtaining of the capacitance of the capacitor.
Chae teaches when measuring capacitance of a capacitor if the measured value is lower than a predetermined threshold a capacitance defect is determined sufficiently disclosed Paragraph 130 “here the value of (B+C)/A exceeds 1.761, had measured capacitance values lower than target capacitance values, and were thus designated as having a capacitance defect”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Childs in view of such that “the capacitor with a defect is identified by the obtaining of the capacitance of the capacitor”.
Substituting and/or combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. In this case it is known means/processes for determining a defect by measuring capacitance.
Claim 15 Childs in view of Tsai and Stucchi the method of Claim 12,
Childs does not explicitly teach wherein the capacitor with a defect is identified when the capacitance of the capacitor is lower than a predetermined threshold.
Chae teaches when measuring capacitance of a capacitor if the measured value is lower than a predetermined threshold a capacitance defect is determined sufficiently disclosed Paragraph 130 “here the value of (B+C)/A exceeds 1.761, had measured capacitance values lower than target capacitance values, and were thus designated as having a capacitance defect”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Childs in view of such that “wherein the capacitor with a defect is identified when the capacitance of the capacitor is lower than a predetermined threshold”.
Substituting and/or combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. In this case it is known means/processes for determining a defect by measuring capacitance.
Conclusion
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/WCT/Examiner, Art Unit 2893
/Britt Hanley/ Supervisory Patent Examiner, Art Unit 2893
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