DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-6, 13, and 14 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The applicant’s claims still contain/recite confusing terminology/limitations.
As best understood by the examiner, after reviewing the applicant’s arguments/remarks (dated August 19, 2026):
“manufactured using a semiconductor manufacturing technology” refers to any object/device made using a process that utilizes a semiconductor material; and
“manufactured using a manufacturing technology other than a semiconductor manufacturing technology” refers to any object/device made using a process that does not utilize semiconductor material, one that uses non-semiconductor material (e.g. metals and dielectrics).
In addition, as best understood from applicant’s disclosure, a “tile” refers to some sort of single/unitary device (e.g. a semiconductor chip).
Therefore, for example, the limitation of claim 1, lines 2-6, specifically:
“Step 1: fabricating a first tile comprising:
a first facility manufactured using a semiconductor manufacturing technology; and
a second facility manufactured using a manufacturing technology other than a semiconductor manufacturing technology”
would refer to a single device (since ‘a first tile’ is the language used) that has both a semiconductor material and some other material that is not a semiconducting material.
The applicant also uses the term “facility” - as best understood by the examiner, this term is used by the applicant to mean “function”.
Paragraph (0005) states, in part “fabricating a first tile comprising a first facility having a first function, using processes best suited to said first function; fabricating a second tile comprising a second facility having a second function substantially different from said first function, using processes best suited to said second function”
Paragraph (0008) states “FIG. 2 illustrates, in stylized cross-section, each of the pre-fabricated function tiles of FIG. 1, before and after integration into a single, coherent package substrate”.
Turning to applicant’s figure 2 (shown below), as an example, depicted are four “tiles”, each having a “facility”.
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Therefore, for example, this drawing figure 2 depicts four devices (i.e. tiles), each having their own specific function (i.e. facility). For example, numeral 102 would be a high-speed input/output device and numeral 108 would be a ‘power’ (possibly a HEMT, a battery, or a capacitor) device.
For purposes of examination, the examiner will interpret “tile” to mean some sort of device, “facility” to mean some sort of intended function, “manufactured using a semiconductor manufacturing technology” is a process that utilizes a semiconductor material; and “manufactured using a manufacturing technology other than a semiconductor manufacturing technology” is a process that utilizes non-semiconductor material (e.g. metals and dielectrics).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 13, and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang et al. (US 10,797,039 B2, hereinafter referred to as ‘Yang’).
As to claim 1, Yang teaches a method comprising the steps of:
Step 1: fabricating a first tile (i.e. semiconductor die 104, see also figures 1a-1c) comprising:
a first facility manufactured using a semiconductor manufacturing technology (semiconductor die 102 using semiconductor material); and
a second facility manufactured using a manufacturing technology other than a semiconductor manufacturing technology (metal layers 112) ; and
Step 2: fabricating a single, integrated package substrate (see figure 13) comprising said first tile.
As to claim 4, Yang teaches a substrate manufactured in accordance with the process of claim 1. See e.g. figure 14.
As to claim 13, Yang teaches
Step 3: fabricating a second tile (e.g. a discrete device, such as a capacitor) comprising:
a third facility manufactured using a manufacturing technology other than a semiconductor manufacturing technology (i.e. the metallic conductive portion of the capacitor); and
a fourth facility manufactured using a manufacturing technology other than a semiconductor manufacturing technology (i.e. the insulation material portion of the capacitor); and
wherein Step 2 is further characterized as fabricating a single, integrated package substrate (310) comprising said first tile and said second tile. See figure 14.
As to claim 2, Yang teaches the steps of testing
Step 4: testing said first tile (i.e. the semiconductor device, see column 4, lines 12-17);
Step 5: testing said second tile (i.e. the discrete device, see column 5, lines 19-40); and
Step 6: if said first tile and said second tile each tests good, fabricating said first tile and said second tile into a single, integrated package substrate (310).
As to claim 14, Yang teaches a method comprising the steps of:
Step 1: fabricating a first tile (i.e. semiconductor die 104, see also figures 1a-1c) comprising:
a first facility manufactured using a semiconductor manufacturing technology (semiconductor die 102 using semiconductor material); and
a second facility manufactured using a manufacturing technology other than a semiconductor manufacturing technology (metal layers 112); and
Step 2: fabricating a second tile (e.g. a discrete device, such as a capacitor) comprising:
a third facility manufactured using a manufacturing technology other than a semiconductor manufacturing technology (i.e. the metallic conductive portion of the capacitor); and
a fourth facility manufactured using a manufacturing technology other than a semiconductor manufacturing technology (i.e. the insulation material portion of the capacitor); and
Step 3: fabricating a single, integrated package substrate (310) comprising said first tile and said second tile. See figure 13.
As to claim 3, Yang teaches the step of:
Step 7: fabricating an advanced package (310) comprising said substrate and at least one redistribution layer (203; as noted by Yang in column 6: “As illustrated, substrate 200 includes one or more insulating layers 203 with conductive layers 204 and 206 on opposite sides of the substrate. Portions of conductive layers 204 and 206 are electrically connected to each other by conductive traces within the conductive layers and conductive vias 208 through substrate 200.” – Yang is describing 203 as a redistribution layer).
As to claims 6 and 5, Yang teaches an advanced package (310) manufactured in accordance with the process of claim 3 and Yang teaches a substrate (310) manufactured in accordance with the process of claim 2. It appears that the applicant’s reference to an “advanced package” and a “substrate” are to the same structure.
Response to Arguments
Applicant’s arguments with respect to the pending claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: see the attached form PTO-892 for pertinent cited art.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Scott B. Geyer (telephone: 571-272-1958). The examiner can normally be reached on Monday to Friday, 10AM - 4PM (ET). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at: http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim (telephone: 571-272-8458). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only.
For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (in U.S.A. or Canada) or 571-272-1000.
/SCOTT B GEYER/ Primary Examiner, Art Unit 2812
