Listed by the USPTO as GEYER, SCOTT B
Tech Center 2800 • Art Units: 2800 2812
This examiner grants 94% of resolved cases
GEYER, SCOTT B has resolved 728 cases in Tech Center 2800 and Art Unit 2800. The allowance rate is 94.2%, and the median time to allowance is 694 days. The interview lift is 4.2%, showing a limited recorded association between interviews and allowance outcomes. The figures support a prosecution plan focused on clear claim presentation and efficient responses.
The principal companies are Taiwan Semiconductor Manufacturing Company, Ltd., Samsung Electronics Co., Ltd., and Intel Corporation. The leading firms are Alliance IP, LLC - Intel, Eschweiler & Potashnik, LLC (TSMC), and Essential Patents Group, LLP. These records identify semiconductor applicants and counsel with recurring experience in the docket.
| App # | Title | Status | Assignee |
|---|---|---|---|
| 18811512 | PASSIVE COMPONENT EMBEDDED SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME | Non-Final OA | SAMSUNG ELECTRONICS CO., LTD. |
| 18662107 | CAPACITOR, SEMICONDUCTOR DEVICE COMPRISING THE CAPACITOR, AND METHOD OF FABRICATING THE CAPACITOR | Non-Final OA | Samsung Electronics Co., Ltd. |
| 18566939 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND ELECTRONIC EQUIPMENT | Non-Final OA | SONY SEMICONDUCTOR SOLUTIONS CORPORATION |
| 18762478 | PACKAGE FORMATION METHODS INCLUDING COUPLING A MOLDED ROUTING LAYER TO AN INTEGRATED ROUTING LAYER | Non-Final OA | Intel Corporation |
| 18409105 | SELF ASSEMBLED MONOLAYER FORMED ON A QUANTUM DEVICE | Non-Final OA | International Business Machines Corporation |
| 18788031 | MULTI-GATE SEMICONDUCTOR DEVICE WITH INNER SPACER AND FABRICATION METHOD THEREOF | Non-Final OA | Taiwan Semiconductor Manufacturing Company, Ltd. |
| 18644209 | CHIP PACKAGE STRUCTURE WITH LID AND METHOD FOR FORMING THE SAME | Non-Final OA | Taiwan Semiconductor Manufacturing Company, Ltd. |
| 18783807 | 3DIC WITH GAP-FILL STRUCTURES AND THE METHOD OF MANUFACTURING THE SAME | Non-Final OA | Taiwan Semiconductor Manufacturing Co., Ltd. |
IP Author analyzes examiner patterns and generates tailored response strategies with the highest chance of allowance.
Build Your Strategy94.2% of resolved applications examined by Scott B Geyer were allowed (728 resolved cases), compared with 69.7% across Art Unit 2800 over the last five years.
This examiner's interview lift is +4.2 percentage points: the difference in allowance rate between resolved applications that had an examiner interview and those that did not.
Applications allowed by Scott B Geyer took 694 days on average from filing to allowance.
Scott B Geyer examines applications in Art Unit 2800 in Tech Center 2800 (Semiconductors, Circuits & Optics).
